JP2995721B2 - Division device and division method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a divider for dividing a binary number of an unsigned number or a signed number and used in a central processing unit of a digital computer.

[0002]

2. Description of the Related Art As a division algorithm in a conventional division device, for example, Kai Hwang, edited by Yasushi Horikoshi, "High-speed operation method of computer" (September 1, 1980, Modern Science Co., Ltd.) PP. Some are shown in section 7.5 (binary non-restoring division). In this division algorithm,
The quotient and remainder are obtained as follows.

First, at the beginning of division, the divisor is subtracted from the dividend to obtain a partial remainder. If the partial remainder is positive, the partial quotient is set to 1, if the partial remainder is negative, 0 is set, and the partial remainder is doubled. (Shift by one bit in the upper bit direction). Thereafter, if the partial remainder obtained by the previous operation is positive, the divisor is subtracted from the multiple of the partial remainder, and if negative, the divisor is added to the multiple of the partial remainder to obtain a new partial remainder. If the partial remainder is positive, the partial quotient is set to 1; if negative, it is set to 0, and the new partial remainder is doubled. This process is repeated by the difference between the number of bits of the dividend and the number of bits of the divisor.

That is, irrespective of the magnitude relationship between the double of the partial remainder and the divisor, if the partial remainder is positive, the divisor is subtracted. If the partial remainder is negative, the divisor is added and the addition / subtraction result is positive. The algorithm is simplified by setting the partial quotient to 1 in the case and 0 in the negative case.
It is possible to increase the division speed and reduce the circuit scale.

By the way, whether the partial remainder is positive or negative is determined as follows.
In addition and subtraction between the divisor and the double of the partial remainder obtained by the previous operation, the addition is performed based on the presence or absence of a carry from the most significant bit excluding the sign bit. That is, the above addition / subtraction is essentially always addition of a positive number and a negative number, and if there is a carry from the most significant bit, the sign bit is always 0. If there is no carry from the bit, the sign bit is always 1 and the result of addition / subtraction can be determined as a negative number.

Further, the above-mentioned division algorithm can be applied only when both the dividend and the divisor are non-negative.
A conventional division device that can perform division between signed numbers is
Absolute value generating means for previously obtaining the absolute values of the dividend and divisor to obtain a non-negative number, absolute value dividing means for obtaining the quotient (absolute value of the quotient) between the non-negative dividend and the divisor, and the dividend and the divisor having different signs. In the case of, the sign of the quotient is determined to be negative, and when the dividend and the divisor have the same sign, the sign determining means for determining the sign of the quotient to be positive, and a sign for converting the absolute value of the quotient to a signed number Number conversion means.

[0007]

However, in the above-mentioned conventional division algorithm, whether the partial remainder is positive or negative is determined as follows.
In addition / subtraction of the divisor with the double of the partial remainder obtained by the previous operation, the addition / subtraction is performed at least one bit larger than the bit width of the divisor in order to perform the addition / subtraction depending on the presence / absence of a carry from the most significant bit excluding the sign bit. Must be done in This is because the partial remainder obtained by the previous operation has the same bit width as the divisor, and the bit width from the most significant bit to the least significant bit in the double (the number shifted by one bit in the upper bit direction) is the divisor This is because the bit width becomes one bit larger than the bit width of the above. Strictly speaking, even when the most significant bit is ignored and addition / subtraction is performed with a divisor bit width, if the value of the most significant bit and the value of the sign bit are the same (both 0 or 1),
The sign of the addition / subtraction result is correctly determined, but if they are not the same (0 and 1, or 1 and 0), the sign is reversed due to a so-called shift overflow, so that the correct sign cannot be determined.

Therefore, the conventional divider has a problem that the circuit width cannot be reduced by shortening the bit width of the addition / subtraction circuit. Further, in order to be able to perform division between signed numbers, in addition to the absolute value dividing means, an absolute value generating means, a sign determining means, a signed number converting means, and a process by these means Because of the necessity of steps, it is also difficult to reduce the circuit scale and to increase the division speed.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a division device and a division method capable of reducing the circuit scale and increasing the division speed.

[0010]

In order to achieve the above object, the present invention relates to a division device for performing division of an unsigned binary number, which has the same bit width as the divisor and has a dividend or a partial remainder of 2. Calculating means for adding and subtracting a multiple and a divisor in accordance with the value of the partial quotient ; shifting means for shifting the result of addition and subtraction to the upper bit side by one bit;
From the next time, the partial quotient from the next
Carry value from means, shift overflow from shift means
At least two of the value of
If one of the values is 1, set it to 1, otherwise set it to 0
And a quotient calculation means .

A division method for performing division of an unsigned binary number, the method comprising: adding and subtracting a double of a dividend or a partial remainder and a divisor with the same bit width as the divisor according to a value of a partial quotient; the Starring a shift step, a partial quotient of the first shifting the subtraction result to the 1-bit high-order bit side
The value of the carry from the calculation step
The quotient is calculated as the carry value,
Value of shift overflow due to shift step, and
1 if at least two of the quotient values are 1
And a partial quotient calculation step of setting the value to 0 otherwise .

A division device for performing division of a signed binary number, wherein a divisor for a partial remainder is calculated by using a value of a partial quotient immediately before the divisor.
Find a new partial remainder by adding and subtracting according to
Arithmetic means, and the sign of the divisor is negative,
If both partial remainders in the previous process are not zero
Is the partial quotient of the inversion of the carry value from the arithmetic means.
Otherwise, the carry from the arithmetic means is
And a partial quotient calculation unit that uses the value as a partial quotient .

A division method for performing a division of a signed binary number, wherein a divisor for a partial remainder is calculated by adding a value of the immediately preceding partial quotient to the partial remainder
Find a new partial remainder by adding and subtracting according to
An operation step, wherein the sign of the divisor is negative and
If the partial remainders in the previous and next processing are not both zero
In this case, the inversion of the value of the carry in the calculation step is included.
Otherwise, the calculation step
And calculating a partial quotient using a carry value as a partial quotient .

[0014]

According to the above arrangement, in the division device or the division method for dividing an unsigned binary number, the first partial quotient is
The carry value of the calculating means (step) is used, and
The partial quotient is the value of the carry of the calculating means (step),
The value of the shift overflow of the shift means (step)
At least two of the previous partial quotient values are 1
If it is 1, set it to 0, otherwise set it to 0.

In a division apparatus or a division method for dividing a signed binary number, the sign of the divisor may be negative.
And the partial remainders in the current and previous processes are both
If not zero, the carry of the arithmetic means (step)
Is the partial quotient, otherwise,
The value of the carry by the calculation means (step) is used as the partial quotient.
You.

[0016]

【Example】

(First Embodiment) FIG. 1 is a block diagram of a division device for dividing unsigned numbers according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a divisor register for holding a divisor.

2 is an input to which the A input (the higher-order bit of the dividend or the partial remainder) and the B input (the divisor) are input, and adds the A input and the B input and outputs the result, or outputs the B signal from the A input. An arithmetic circuit that subtracts the input and outputs the result, or transfers the A input as it is and outputs it. The addition and subtraction are performed with the same bit width as that of the divisor register 1.
The carry (ACRY) from the most significant bit is output.

Reference numeral 3 denotes a first shifter which shifts the output (partial remainder) of the arithmetic circuit 2 by one bit in the upper bit direction, or transfers and outputs the output as it is. When the first shifter 3 shifts, a shift overflow value of the second shifter 5 described later is inserted into the least significant bit. Reference numeral 4 denotes a first register which temporarily holds the upper bits of the dividend or the output of the first shifter 3 (the upper bits of a multiple of 2 times the partial remainder), and outputs the value as an A input of the arithmetic circuit 2 via the register R2. is there.

Reference numeral 5 denotes a second shifter which shifts the input value by one bit in the upper bit direction, or transfers and outputs the value as it is. When the second shifter 5 shifts, a partial quotient Q (n) given from the control circuit 8 described later is sequentially inserted into the least significant bit. Reference numeral 6 denotes a second register which temporarily holds the lower bits of the dividend or the output of the second shifter 5 (lower bits of a multiple of two times the partial remainder) and inputs the value to the second shifter 5 again via the register R2. . The second register 6 also serves as a register for holding a quotient.

Reference numeral 7 denotes a shift overflow (S) from the first shifter 3.
CRY), and is a shift-overflow holding register that outputs via a register R2. Numeral 8 has a counter (not shown) for counting the number of processing steps (n). The number of processing steps (n), carry from the most significant bit of the arithmetic circuit 2 (ACRY), and the value of the shift overflow holding register 7 ( SCRY) and the value of the least significant bit of the second register 6 (the previous partial quotient Q (n-1)).
(OPR), the number of shifts of the first shifter 3 (S
FT1), and the number of shifts of the second shifter 5 (SFT2)
, And generates an insertion value (partial quotient Q (n)) to the least significant bit when the second shifter 5 shifts by 1 bit.

More specifically, the control circuit 8 performs control as shown in FIG. 2 for each processing step. That is, if the OPR column in FIG.
Input transfer is instructed to the arithmetic circuit 2 to add the A and B inputs if "A + B", and to subtract the B input from the A input if "AB". If the column of SFT1 or SFT2 is "L1", it instructs the first shifter 3 or the second shifter 5 to shift 1 bit in the upper bit direction, and if "0", shifts 0 bits, that is, transfers. Furthermore, Q
If the field (n) is "ACRY", the carry from the most significant bit of the arithmetic circuit 2 is carried out. If the value is "Z", the value determined by the following equation (1) is added to the least significant bit of the second shifter 5 by the partial quotient Q. Insert as (n). Here, in the expression (1), “•” represents a bit AND, and “+” represents a bit OR.

Z = ACRY · (Q (n−1) + SCRY) + Q (n−1) · SCRY (1) Z is at least one of Q (n−1), SCRY and ACRY When any two values are 1, the value becomes 1, indicating that the partial remainder is positive. That is, as shown in FIG. 2, when n = 1 to 2, Q (n-1) = 0
When the partial remainder of the previous processing step is negative, the divisor (B) is added, while when Q (n-1) = 1 (the partial remainder of the previous processing step is positive), the divisor is subtracted. Assuming that the above subtraction is the addition of the two's complement (-B) of the divisor, the value of the bit one bit higher than the bit width of the divisor in the addend (B or -B) is Q (n-1) 0 when Q = 0, and 1 when Q (n-1) = 1. Also, SCR
Y is the value of the bit one bit higher than the bit width of the divisor in the augend (A), and ACRY is the carry to the bit one bit higher than the bit width of the divisor in the addition of the bit width of the divisor. is there.

Therefore, although the addition by the arithmetic circuit 2 is performed only with the bit width of the divisor, the addition from the bit one bit higher than the bit width of the divisor in the case of adding the bit width one bit larger than the bit width of the divisor. The presence / absence of a carry (positive / negative of the partial remainder) is determined by determining whether at least any two values of Q (n-1), SCRY, and ACRY are 1 (Z
= 1).

Therefore, the sign of the partial remainder can be accurately determined from the value of Z, and by setting this Z as the partial quotient Q (n), the correct partial quotient Q according to the sign of the partial remainder can be obtained.
(n) is obtained. In many cases, the divisor register 1, the arithmetic circuit 2, the first shifter 3, the first register 4, the second shifter 5, the second register 6, and the connection lines between them are all 16 bits or 32 bits. The data width is a power of. However, for the sake of simplicity, the description will be made assuming that the data width is 3 bits. Note that in principle, any data width may be used.

The first register 4, the second register 6,
The shift overflow holding register 7 holds the input data in synchronization with the clock signal φ1, and the divisor register 1 and each register R2 hold the input data in synchronization with the clock signal φ2. Actually, in addition to the above, there are provided a means for detecting a quotient overflow, a means for normalizing the divisor, and the like.

The operation of the dividing device according to the present embodiment configured as described above under the control of the control circuit 8 will be described. (1) Before Starting Processing Step (Initialization Processing) First, the value (n) of the counter inside the control circuit 8 is cleared to 0, and the divisor of the 3-bit unsigned number is stored in the divisor register 1. When the dividend is a 6-bit unsigned number, the upper 3 bits are stored in the first register 4.
While the lower three bits are stored in the second register 6 respectively, if the dividend is a 3-bit unsigned number, the first register 4 is cleared to 0 and the dividend is stored in the second register 6. (2) First Processing Step (n = 0) First, the value held in the first register 4 and the divisor held in the divisor register 1 are stored in the A
Calculation is performed by inputting to the input and the B input. The calculation at this time is a subtraction of the B input from the A input as shown in the OPR column of FIG.

Next, the operation result of the above operation and the value of the second register 6 are shifted by one bit in the upper bit direction by the first shifter 3 or the second shifter 5, respectively. Two are stored in the register 6. At this time, the shift overflow holding register 7 stores a shift overflow (SCRY) from the most significant bit of the first shifter 3.
Is stored in the least significant bit of the first shifter 3, and a shift overflow from the most significant bit of the second shifter 5 is inserted.
As shown in the column of Q (n) in FIG. 2, the carry (ACRY) of the arithmetic circuit 2 is given from the control circuit 8 and inserted into the least significant bit of the second shifter 5.

Further, the value (n) of the counter inside the control circuit 8 is incremented by one. (3) Second and third processing steps (n = 1 to 2) First, the value held in the first register 4 and the divisor held in the divisor register 1 are stored in the A
Calculation is performed by inputting to the input and the B input. At this time, as shown in the OPR column of FIG. 2, if the value of the least significant bit of the second register 6 (the previous partial quotient Q (n-1)) is 0, the A input and the B input If the addition is 1, then the B input is subtracted from the A input.

Next, similarly to the first processing step, the operation result and the value of the second register 6 are shifted by one bit in the upper bit direction by the first shifter 3 or the second shifter 5, respectively. It is stored in one register 4 or the second register 6. At this time, as in the first processing step, the shift overflow holding register 7 stores the first shifter 3
, The shift overflow (SCRY) from the most significant bit of the first shifter 3 is stored in the least significant bit of the first shifter 3.
The shift overflow from the most significant bit of the second shifter 5 is inserted. The least significant bit of the second shifter 5, as shown in the column of Q (n) in FIG. From the value of the least significant bit (Q (n-1)) of the second register 6 and the value of the shift overflow holding register 7 (SCRY), the value of Z obtained by the above equation (1) is given from the control circuit 8 and inserted. Is done.

Further, the value (n) of the counter inside the control circuit 8 is incremented by 1, and the above processing is repeated until the value becomes 3. (4) Fourth Processing Step (n = 3) First, similarly to the second and third processing steps, the value held in the first register 4 and the divisor held in the divisor register 1 are each calculated by an arithmetic circuit. 2 and the value of the least significant bit (Q (n-1)) of the second register 6
Addition or subtraction is performed according to.

Next, the operation result is directly input to the first shifter 3.
, While the value of the second register 6 is shifted by one bit in the upper bit direction by the second shifter 5, and the shift result is stored in the second register 6. In this case, the shift overflow from the most significant bit of the second shifter 5 is discarded without being inserted into the least significant bit of the first shifter 3, but the least significant bit of the second shifter 5 has the second least significant bit.
To the third processing step, the carry (A
CRY), the value of the least significant bit of the second register 6, and the value of the shift overflow holding register 7 (SCRY), the value of Z determined by equation (1) is given from the control circuit 8 and inserted. That is, the partial quotient Q (n) is obtained and stored in the second shifter 5 in the same manner as in the second and third processing steps. However, since the operation result output from the operation circuit 2 is the final remainder, it is doubled. Without being stored in the first register 4.

The value (n) of the counter inside the control circuit 8 is incremented by one. (5) Fifth processing step (n = 4) The value held in the first register 4 and the divisor held in the divisor register 1 are input to the A input and the B input of the arithmetic circuit 2, respectively, to perform the operation. Do. At this time, as shown in the OPR column of FIG. 2, if the value of the least significant bit (Q (n-1)) of the second register 6 is 0, the A input and the B input are added.
Then, the A input is transferred. That is, when the final remainder is negative, the divisor is added to correct the final remainder.

The operation result and the value of the second register 6 are stored in the first register 4 or the second register 6 via the first shifter 3 or the second shifter 5 as they are. After the above processing is performed, the value stored in the first register 4 is the remainder to be determined, and the value stored in the second register 6 is the quotient to be determined.

FIG. 3 shows a specific calculation process performed by the above processing in a handwriting format. Here, “X” and “C” in the figure respectively indicate carry (ACRY) to a bit one bit higher than the bit width of the divisor in the addition of the arithmetic circuit 2, and the underline indicates the first shifter 3. Overflow from the most significant bit of (SCRY)
Is shown.

In the above example, the second register 6 is used for storing the dividend or partial remainder and storing the quotient, but the register for storing the quotient may be provided independently. In this case, it is not necessary to divide the first shifter 3 and the second shifter 5, and it is easy to arbitrarily set the number of quotient bits. (Second Embodiment) FIG. 4 is a block diagram of a division device for performing division between signed numbers according to a second embodiment of the present invention. This division device rounds the quotient in the negative direction and makes the sign of the remainder the same as the sign of the divisor. Specifically, for example, when the dividend is -10 and the divisor is 3, the quotient is -4 and the remainder is 2. In the second embodiment,
Components having the same functions as those of the first embodiment are denoted by the corresponding reference numerals, and description thereof is omitted.

In FIG. 4, reference numerals 15 and 19 denote a second shifter and a third shifter which shift the input value by one bit in the higher-order bit direction or transfer and output the input value as it is.
Reference numeral 6 denotes a second register which temporarily holds the lower bits of the dividend or the output of the second shifter 15 (lower bits of a multiple of two times the partial remainder) and inputs the value to the second shifter 15 again.
Is a register for holding a quotient. That is, different from the first embodiment, the means for shifting or holding the dividend and the like and the means for shifting or holding the quotient are provided independently. When the second shifter 15 shifts, a value “0” is inserted into the least significant bit. When the third shifter 19 shifts, a partial quotient Q (n) given from a control circuit 18 described later.
Are sequentially inserted into the least significant bit.

Reference numeral 21 denotes a dividend code register that holds the sign (S1) of the dividend, that is, the value of the most significant bit of the dividend. Reference numeral 22 denotes a first zero detection circuit that outputs 1 as the value (Z1) when the values held in all the bits of the first register 14 are 0. 23 is the second register 1
This is a second zero detection circuit that outputs 1 as the value (Z2) when the value held in all the bits of 6 is 0.

Reference numeral 24 denotes a first zero detection holding register for holding the detection result of the first zero detection circuit 22. Reference numeral 25 denotes a second zero detection holding register that holds the detection result of the second zero detection circuit 23. Reference numeral 18 has a counter (not shown) for counting the number of processing steps (n) therein. The number of processing steps (n), the value of the dividend code register 21 (S1), and the most significant bit of the divisor register 11 which is the sign of the divisor are shown. Value (S
2), carry from the most significant bit of the arithmetic circuit 12 (AC
RY), the value of the least significant bit of the third register 20 (the previous partial quotient Q (n-1)), the first zero detection circuit 22, the second zero detection circuit 23, and the first zero detection hold A register 24;
Based on the detection result with the second zero detection holding register 25 or the held contents (Z1, Z2, PZ1, PZ2), the type of operation of the arithmetic circuit 12 (OPR), the number of shifts of the first shifter 13 (SFT1), Number of shifts of the second shifter 15 (SFT
2) and a control circuit for instructing the shift number (SFT3) of the third shifter 19 and generating an insertion value (partial quotient Q (n)) to the least significant bit when the third shifter 19 shifts by 1 bit. is there.

FIG. 5 is an explanatory diagram showing specific control contents for each processing step of the control circuit 18 as in FIG. 2 of the first embodiment. "ACRY" in the column of Q (n) in FIG.
And "ACRY" with an overline indicates that the carry from the most significant bit of the arithmetic circuit 12 or the bit inverted value thereof is inserted into the least significant bit of the third shifter 19 as a partial quotient Q (n-1). .

The divisor register 11, the arithmetic circuit 12,
A first shifter 13, a first register 14, a second shifter 15,
Second register 16, third shifter 19, third register 2
0, the first zero detection circuit 22, the second zero detection circuit 23, and the connection lines between them have a data width of 3 bits. The operation of the dividing device configured as described above according to the present embodiment based on the control of the control circuit 18 will be described. (1) Before the start of the processing step (initialization processing) First, the value (n) of the counter inside the control circuit 18, the values of the first zero detection holding register 24 and the second zero detection holding register 25 (PZ1, PZ2) Is cleared to 0, and the divisor of the 3-bit signed number is stored in the divisor register 11. If the dividend is a 6-bit signed number, the upper 3 bits are stored in the first register 14 and the lower 3
While the bits are stored in the second register 16 respectively, if the dividend is a 3-bit signed number, the value of the sign bit of the dividend is copied to all bits of the first register 14 and the dividend is stored in the second register 16. To be stored. (2) First Processing Step (n = 0) First, the value held in the first register 14 and the divisor held in the divisor register 11 are respectively calculated by the arithmetic circuit 1
2 and input to the A and B inputs to perform the operation. At this time, as shown in the OPR column of FIG. 5, if the value (S1) of the dividend code register 21 and the value of the most significant bit (S2) of the divisor register 11 are the same value, the input from the A input to the B The input is subtracted, and if different, the A and B inputs are added.

Next, the operation result of the above operation, the value of the second register 16 and the value of the third register 20 are stored in the first shifter 13, the second shifter 15, and the third shifter 19, respectively.
Shifts one bit in the upper bit direction, and stores the shift result in the first register 14, the second register 16, or the third register 20, respectively. At this time, the shift overflow from the most significant bit of the second shifter 15 is inserted into the least significant bit of the first shifter 13, the value “0” is inserted into the least significant bit of the second shifter 15, and As shown in the column of Q (n) in FIG. 5, the carry (ACRY) of the arithmetic circuit 12 or its bit inverted value is given from the control circuit 18 and inserted into the least significant bit of the three shifters 19. .

More specifically, the value (S2) of the most significant bit of the divisor register 11 is 1, and at least one of the detection results (Z1, Z2) of the first zero detection circuit 22 and the second zero detection circuit 23 is 0. And the first zero detection holding register 2
4 and second zero detection holding register 25 (PZ
1, PZ2) is 0, a bit inversion value of the carry (ACRY) of the arithmetic circuit 12 is inserted, otherwise, the carry (AC) of the arithmetic circuit 12 is inserted.
RY) is inserted as it is.

Further, the value (n) of the counter inside the control circuit 18 is incremented by one. (3) Second and third processing steps (n = 1 to 2) First, the value held in the first register 14 and the divisor held in the divisor register 1 are calculated by the arithmetic circuit 12
Is input to the A input and the B input. The operation at this time is as shown in the OPR column of FIG.
If the value of the least significant bit of 0 (the previous partial quotient Q (n-1)) is 0
If so, the A input and the B input are added, and if 1, the A input and the B input are subtracted.

Next, similarly to the first processing step, the operation result and the values of the second register 16 and the third register 20 are respectively shifted by the first shifter 13, the second shifter 15 or the third shifter 19 to the upper bit. Shift one bit in the direction
The shift result is stored in the first register 14, the second register 16, or the third register 20. At that time, the first
Similarly to the processing step, the shift overflow from the most significant bit of the second shifter 15 is inserted into the least significant bit of the first shifter 13, and the least significant bit of the second shifter 15 is
The value "0" is inserted, and the least significant bit of the third shifter 19 is controlled by the carry (ACRY) of the arithmetic circuit 12 or its bit inverted value, as shown in the column of Q (n) in FIG. Provided from circuit 18 and inserted.

Further, the value (n) of the counter inside the control circuit 18 is incremented by one, and the above processing is repeated until the value becomes three. (4) Fourth Processing Step (n = 3) First, similarly to the second and third processing steps, the value held in the first register 14 and the divisor held in the divisor register 11 are each calculated by an arithmetic circuit. 12 to the A and B inputs, and the value of the least significant bit (Q
Addition or subtraction is performed according to (n-1)).

Next, the operation result is directly input to the first shifter 1.
3, while the value of the second register 16 and the value of the third register 20 are stored in the first register 14.
The data is shifted by one bit in the upper bit direction by the fifth or third shifter 19 and the shift result is stored in the second register 16 or the third register 20. In this case, the shift overflow from the most significant bit of the second shifter 15 is discarded without being inserted into the least significant bit of the first shifter 13, but the least significant bit of the second shifter 15 includes the second to second bits. The value “0” is inserted in the same manner as in the third processing step, and the least significant bit of the third shifter 19 is also the value (S2) of the most significant bit of the divisor register 11, similarly to the second and third processing steps, And the first zero detection circuit 22, the second zero detection circuit 23, the first zero detection holding register 24, and the second zero detection holding register 25 for the detection results or holding contents (Z1, Z2, PZ1, PZ1).
According to 2), the carry (ACRY) of the arithmetic circuit 12 or the bit inverted value thereof is given from the control circuit 18 and inserted. That is, the partial quotient Q (n) is obtained and stored in the second shifter 15 in the same manner as in the second and third processing steps. However, since the operation result output from the operation circuit 12 is the final remainder, it is doubled. Without being stored in the first register 14.

Further, the value (n) of the counter inside the control circuit 18 is incremented by one. (5) Fifth processing step (n = 4) The value held in the first register 14 and the divisor register 1
The divisor held at 1 is represented by A
Calculation is performed by inputting to the input and the B input. The operation at this time is
As shown in the OPR column of FIG. 5, if the value of the least significant bit (Q (n-1)) of the third register 20 is 0, the A and B inputs are added, and if it is 1, the A input is transferred. That is, when the final remainder is negative, the divisor is added to correct the final remainder.

Further, the operation result, the values of the second register 16 and the third register 20 are directly passed through the first shifter 13 or the second shifter 15 or the third shifter 19, respectively, and the first register 14 and the third register The data is stored in the second register 16 or the third register 20. After the above processing is performed, the value stored in the first register 14 is the remainder to be determined, and the value stored in the third register 20 is the quotient to be determined.

FIG. 6 shows a specific calculation process performed by the above-described processing in a handwriting format. Here, the first
As in the embodiment, “X” and “C” in the figure indicate carry to one bit higher than the bit width of the divisor in the addition of the arithmetic circuit 2 (ACRY), respectively. The shift overflow (SCRY) from the most significant bit of one shifter 3 is shown.

In the second embodiment, the third shifter 19 and the third register 20 are provided, and the partial quotient Q (n) generated by the control circuit 18 is inserted into the least significant bit of the third shifter 19. Is stored in the third register 20, but without providing the third shifter 19 and the third register 20, the partial quotient Q (n) generated by the control circuit 18 is inserted into the least significant bit of the second shifter 15. And the second zero detection circuit 23 detects all of the values input to the second register 16 except for the partial quotient inserted and stored by the second shifter 15. Is output as the value (Z2) when the bit is zero. In this case, the quotient is stored in the second register 16 when the fifth processing step ends. (Third Embodiment) As a modification of the second embodiment, the quotient is set to 0.
A divider will be described in which the sign of the remainder is rounded in the direction and the sign of the remainder is the same as the sign of the dividend. That is, for example, if the dividend is -1
When 0 and the divisor is 3, the quotient is -3 and the remainder is -1.

This division device is different from the division device of the second embodiment in the control contents of the control circuit 18. That is, as shown in FIG. 7, in the first processing step (n = 0),
The value (Q (n-1)) to be inserted into the least significant bit of the third shifter 19
), If the most significant bit (S2) of the divisor register 11 is 1 regardless of the value of the output (Z1) of the first zero detection circuit 22 and the output (Z2) of the second zero detection circuit 23, If the inverted value of the carry is 0, the carry of the arithmetic circuit 2 is given from the control circuit 18.

The second and third processing steps (n = 1 to
2) and the fourth processing step (n = 3)
The value (Q (n-1)) to be inserted into the least significant bit of the third shifter 19
), The value (S1) of the dividend code register 21 is 0
And the most significant bit (S2) of the divisor register 11 is 1, the value (S1) of the dividend code register 21 is 1, the most significant bit of the divisor register 11 is 0, and Z1 · Z
When 2 + PZ1 · PZ2 is 1, and when the value (S1) of the dividend code register 21 is 1 and the most significant bit of the divisor register 11 is 1 and Z1 · Z2 + PZ1 · PZ2 is 0, the carry of the arithmetic circuit 12 is carried out. Is supplied from the control circuit 18, while in other cases, the carry of the arithmetic circuit 12 is supplied from the control circuit 18.

In the fifth processing step (n = 4),
The value held in the first register 14 and the divisor register 1
If the value (S1) of the dividend code register 21 and the most significant bit (S2) of the divisor register 11 have the same value as an operation of the divisor held in 1 by the arithmetic circuit 12, the third register 20 Least significant bit (Q (n-
If 1)) is 0, the A input and the B input are added, and if it is 1, the A input is transferred. On the other hand, if the value is different, if the least significant bit of the third register 20 is 0, the A input is transferred. , 1
Then, the B input is subtracted from the A input.

The quotient to be obtained is a value stored in the third register 20 when the dividend and the divisor have the same sign, but is stored in the third register 20 when the dividend and the divisor have different signs. 1 is added to the value, and the result is again stored in the third register 20.
Is the quotient to be found. In other words, the quotient and remainder of the signed number can be obtained with the same number of processing steps as that in the case of dividing an unsigned number or by one more processing number and without a significant increase in hardware. The addition of 1 is performed by adding (incrementing) 1 to the third shifter 19 in addition to the shift and transfer functions.
The function may be performed with a function to perform the calculation, the arithmetic circuit 12 may be used, or another adder (not shown) may be used.

FIG. 8 shows a specific calculation process performed by the above processing in a handwriting format. In the second and third embodiments, an example has been described in which the quotient is obtained as a two's complement representation number. However, the quotient may be obtained as a redundant binary representation number.

In each of the embodiments, an example has been described in which the dividing device is configured by hardware. However, the present invention is not limited to this. For example, basic circuits corresponding to the above blocks and basic circuits for controlling the operations of these circuits are provided. It can also be configured by a general instruction sequence.

[0057]

As described above, according to the present invention,
In a division apparatus or a division method for performing division of an unsigned binary number, a carry value by addition / subtraction according to a value of a partial quotient between a dividend or a multiple of a partial remainder and a divisor, and one bit higher than an addition / subtraction result Since a new partial quotient is obtained based on the value of the shift overflow due to shifting to the bit side and the value of the previous partial quotient, an accurate quotient can be obtained by addition and subtraction with the same bit width as the divisor, and This has the effect of reducing the circuit scale and increasing the division speed.

Further, in a division apparatus or a division method for dividing a signed binary number, a carry value or a divisor value obtained by addition / subtraction of a multiple of a dividend or a partial remainder and a divisor according to a value of a partial quotient is provided. Since the new partial quotient is determined based on the sign of the dividend and the dividend, the value of the previous partial quotient, and whether at least one of the latest addition / subtraction result or the previous addition / subtraction result is 0, the dividend It is possible to obtain a signed quotient without calculating the absolute value of the divisor or converting the absolute value of the quotient to a signed number, again reducing the circuit scale and increasing the division speed. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a division device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing control contents of a division device.

FIG. 3 is an explanatory diagram showing a specific example of a division process.

FIG. 4 is a block diagram illustrating a configuration of a division device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing the control contents of the division device.

FIG. 6 is an explanatory diagram showing a specific example of a division process.

FIG. 7 is an explanatory diagram showing control contents of a divider in a third embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a specific example of a division process.

[Description of Signs] R2 register 1 divisor register 2 operation circuit 3 first shifter 4 first register 5 second shifter 6 second register 7 shift overflow holding register 8 control circuit 11 divisor register 12 operation circuit 13 first shifter 14 first Register 15 Second shifter 16 Second register 18 Control circuit 19 Third shifter 20 Third register 21 Dividend sign register 22 First zero detection circuit 23 Second zero detection circuit 24 First zero detection holding register 25 Second zero detection holding register

Claims (16)

(57) [Claims] 1. A division device for performing division of an unsigned binary number, the division device having the same bit width as the divisor, and adding and subtracting a dividend or a multiple of a partial remainder and a divisor according to a value of a partial quotient. Arithmetic means; shift means for shifting the result of addition / subtraction to the upper bit side by one bit; and a first partial quotient as a carry value from the arithmetic means;
Subsequent partial quotients are calculated as carry values from the arithmetic means,
Value of the shift overflow from the shift means and the previous partial quotient
If at least two of the values are 1, then 1
And a partial quotient calculation unit that otherwise sets the division quotient to 0 . 2. A division method for performing division of an unsigned binary number, comprising: an operation step of adding / subtracting a dividend or a multiple of a partial remainder and a divisor with the same bit width as the divisor according to a value of a partial quotient. A shift step of shifting the result of addition / subtraction to the upper bit side by 1 bit, and a carry of the first partial quotient by the calculation of the calculation step.
Value and the next and subsequent partial quotients
Value due to carry, overflow due to shift step
At least two of the value of
If one of the values is 1, set it to 1, otherwise set it to 0
A division method comprising : a quotient calculation step . 3. A divisor holding means for holding a divisor of an unsigned number, adding the first and second inputs and outputting the result, or outputting the result from the first input to the second input. Calculating means for performing the subtraction and outputting the result or transferring and outputting the first input as it is; first shifting means for shifting the output of the calculating means by one bit in the upper bit direction or transferring the output as it is; At the start of the division process, the upper part of the word length equal to the word length of the divisor holding unit of the unsigned number dividend is held, and during execution of the process, the output of the first shift unit is held. At the end, the first data holding means for holding the remainder; At the start of the processing, the remaining lower part of the dividend is held, and during the processing, the lower part of the dividend shifted in the upper bit direction is stored. Part of the quotient And at the end of the processing, a second data holding means for holding a quotient, and shifting the value held by the second data holding means by one bit in the higher-order bit direction or transferring the result as it is, and returning the result again. A second shift means for storing in the second data holding means, a third data holding means for holding a shift overflow from the most significant bit in the first shift means, and a counting means therein, When the counting means indicates the start of the processing, subtraction is instructed, and when the counting means indicates that the processing is from the start to the end, the value of the least significant bit of the second data holding means is 0 indicates addition, while 1 indicates subtraction, and when the counting means indicates the end of processing, addition is instructed if the value of the least significant bit of the second data holding means is 0. On the other hand, if it is 1, it instructs the transfer of the first input, and instructs the first shift means to shift one bit in the upper bit direction when the counting means indicates that the processing is not the end or the immediately preceding processing. When the counting means indicates the end of the processing or the processing immediately before, the transfer is instructed. When the counting means indicates the start of the processing, the digit in the arithmetic means is instructed to the second shift means. When a 1-bit shift in the direction of the upper bit for instructing the carry to be inserted in the least significant bit is indicated, and the counting means indicates that the processing is between the start and the end of the processing, the carry in the arithmetic means and the second data holding of the values held value of the least significant bits and the third data holding means means
If at least two of the values are 1, then 1;
Control means for instructing a one-bit shift in the upper bit direction in which a value to be set to 0 is inserted in the least significant bit if the counting means indicates the end of processing, and The value held in the divisor holding means and the value held in the divisor holding means are respectively stored in the first
And a second input, the value to be inserted into the least significant bit of the first shift means is a shift overflow from the most significant bit in the second shift means, and the operation in the arithmetic means and the first shift means and the A division apparatus characterized in that a shift in the two-shift means is repeated a number of times equal to the difference between the number of bits of the dividend and the number of bits of the divisor, thereby obtaining a quotient and a remainder. 4. At the start of the division process, the dividend of the unsigned number is divided into an upper part of the word length equal to the word length of the divisor of the unsigned number and a remaining lower part, each of which is a first value or a second value. An initial setting step to hold the value of the above, a counting step of counting the number of times of the repetitive processing, and when the counting step indicates the start of the processing, the divisor is subtracted from the first value, and the processing of the processing is performed by the counting step. When it is indicated from the start to the end, if the least significant bit of the second value is 0, the first value and the divisor are added. When the divisor is reduced and the counting step indicates the end of the process, an arithmetic step of adding the first value and the divisor if the least significant bit of the second value is 0; When it is indicated that the process is not the end of the process or the process immediately before the end, the shift overflow from the most significant bit in the second shift step is inserted into the least significant bit, and the value obtained in the operation step is shifted toward the upper bit. A first shift step of shifting by one bit to make the shift result a new first value; and a shift carry storage for holding a shift overflow from the most significant bit in the first shift step as a third value. When the start of the process is indicated by the step and the counting step, the carry in the operation step is inserted into the least significant bit, and the second value is shifted by one bit in the direction of the higher bit, and the shift result is converted into a new result. The second value,
When the counting step indicates that it is between the start and the end of the processing, the carry in the calculation step, the least significant bit of the second value, and the third value in the step immediately before the current step Of the
1 if at least two values are 1; otherwise
A second shift step of inserting a value to be 0 into the least significant bit and shifting the second value by one bit in the direction of the higher bit to make the shift result a new second value; On the basis of the counting by the counting step, during the period from the start to the end of the processing, the calculation step, the first shift step, the shift carry storage step, and the second shift step are performed by the number of bits of the dividend. And a first value and a second value obtained by repeating the number of times equal to the difference between the number of bits and the number of bits of the divisor, respectively, as a remainder and a quotient, respectively. 5. A division device for performing division of a signed binary number, wherein a divisor is added to or subtracted from a partial remainder in accordance with a value of a previous partial quotient.
Calculating means for obtaining a new partial remainder by performing the calculation, and performing the current and previous processing when the sign of the divisor is negative.
If both partial remainders are not zero,
The inversion of the carry value from the means is used as the partial quotient,
In this case, the value of the carry from the arithmetic means is used as a partial quotient.
And a partial quotient calculating means. 6. A division method for performing a division of a signed binary number, wherein a divisor is added to or subtracted from a partial remainder in accordance with a value of an immediately preceding partial quotient.
Calculating the new partial remainder by performing the calculation, and performing the current and previous processing when the sign of the divisor is negative.
If both partial remainders are not zero,
The inversion of the carry value by the step is used as the partial quotient,
If not, the value of the carry in the above calculation step is
A partial quotient calculation step of dividing the quotient. 7. A division device that divides a signed binary number
So, The divisor for the partial remainder is adjusted according to the value of the previous partial quotient.
Calculating means for obtaining a new partial remainder by calculating For the first partial quotation, If the sign of the divisor is negative, carry from the arithmetic means
Is the partial quotient, otherwise the above
The value of the carry from the arithmetic means is used as the partial quotient, and
About the quotient, If the sign of the divisor is negative and the sign of the dividend is non-negative,
Or Whether the sign of the divisor is non-negative and the sign of the dividend is negative
Either the current remainder or the partial remainder in the previous process
Is zero or The sign of the divisor is negative and
The sign of the divisor is negative and the current and previous processing
If both partial remainders are not zero, Inversion of the value of the carry from the arithmetic means is a partial quotient, Otherwise, the carry value from the arithmetic means is
And a partial quotient calculating means for setting a partial quotient.
Divider. Claim 8. In the division method of dividing a signed binary number
So, The divisor for the partial remainder is adjusted according to the value of the previous partial quotient.
Calculation step for obtaining a new partial remainder by calculating
When, For the first partial quotation, When the sign of the divisor is negative,
The inversion of the carry value is used as the partial quotient;
The value of the carry in the notation step is a partial quotient, For the next and subsequent partial quotations, If the sign of the divisor is negative and the sign of the dividend is non-negative,
Or Whether the sign of the divisor is non-negative and the sign of the dividend is negative
Either the current remainder or the partial remainder in the previous process
Is zero or The sign of the divisor is negative, and the sign of the dividend is negative,
Both partial remainders in current and previous processing are zero
If not, The inversion of the value of the carry in the calculation step is a partial quotient.
And Otherwise, the carry of the calculation step
And calculating a partial quotient using the value as a partial quotient.
Characteristic division method. 9. At the start of the processing, the dividend of the signed number is divided into an upper part of the word length equal to the word length of the divisor of the signed number and the remaining lower part, each of which is a first value or a second value. An initial setting step of holding as a value, a counting step of counting the number of repetitive processes, and when the counting step indicates the start of processing, if the dividend and the divisor have the same sign, the divisor from the first value If the sign is a different sign, the first value and the divisor are added. When the counting step indicates that the processing is from the start to the end, the least significant bit of the second value is set to 0. If the first value and the divisor are added, the divisor is subtracted from the first value if 1, and the end of the processing is indicated by the counting step, the least significant bit of the second value is Then, an operation step of adding the first value and the divisor, and when the counting step indicates that the processing is not the end of the processing or the processing immediately before the end, the shift overflow from the most significant bit in the second shift step is performed. A first shift step of inserting into the least significant bit and shifting the value obtained in the operation step by one bit in the direction of the higher order bit and setting the shift result as a new first value; and terminating the processing by the counting step If not, the carry in the operation step or its inverted value is inserted into the least significant bit, and the second value is shifted by one bit in the direction of the upper bit, and the shift result is converted into a new second value. A second shift step, wherein the value to be inserted into the least significant bit in the second shift step is The sign of the number is negative and the portion of any of the first value or the second value in the current and previous process, except for the one inserted in the least significant bit by the previous step When any one of the bits is 1, the carry in the operation step is inverted, otherwise, the carry in the operation step is performed, and based on the count in the counting step, from the start to the end of the process, A first value and a second value obtained by repeating the operation step, the first shift step, and the second shift step a number of times equal to the difference between the number of bits of the dividend and the number of bits of the divisor. Is a remainder and a quotient, respectively. 10. At the start of the process, the dividend of the signed number is divided into an upper part of the word length equal to the word length of the divisor of the signed number and the remaining lower part, each of which is a first value or a second value. An initial setting step of holding as a value, a counting step of counting the number of repetitive processes, and when the counting step indicates the start of processing, if the dividend and the divisor have the same sign, the divisor from the first value If the sign is a different sign, the first value and the divisor are added, and when the counting step indicates that the processing is from the start to the end, if the least significant bit of the third value is 0, For example, while adding the first value and the divisor, if 1, the divisor is subtracted from the first value, and when the end of processing is indicated by the counting step, the least significant bit of the third value is set to 0. If the calculation step indicates that the processing is not the end of the processing or the processing immediately before the counting step, the shift overflow from the most significant bit in the second shift step is minimized. A first shift step of inserting the value obtained in the arithmetic step by one bit in the direction of the upper bit while shifting the value obtained in the arithmetic step to a new first value, and the counting step does not end the processing. A second shift step of inserting 0 into the least significant bit and shifting the second value by one bit in the direction of the higher bit to make the shift result a new second value; When the counting step indicates that the processing is not completed, the carry in the calculation step or its inverted value is changed to the lowest order. And a third shift step of inserting the third value by one bit in the direction of the higher bits and making the shift result a new third value. When the value of the divisor is negative and any of the bits of the first value or the bit of the second value in the current and previous processing is 1, The carry in the calculation step is inverted, otherwise, the carry in the calculation step is based on the count in the counting step, from the start to the end of the processing, the calculation step and the first The shift step, the second shift step, and the third shift step are repeated a number of times equal to the difference between the number of bits of the dividend and the number of bits of the divisor. A first value and a third value obtained as a remainder and a quotient, respectively. 11. A divisor holding means for holding a divisor of a signed number, adding to the first and second inputs and outputting the result, or outputting the result of the first input to the second input. Calculating means for performing the subtraction and outputting the result or transferring and outputting the first input as it is; first shifting means for shifting the output of the calculating means by one bit in the upper bit direction or transferring the output as it is; At the start of the division process, the upper part of the word length equal to the word length of the divisor holding unit of the dividend of the signed number is held, and during the execution of the process, the output of the first shift unit is held. At the end, the first data holding means for holding the remainder; At the start of the processing, the remaining lower part of the dividend is held, and during the processing, the lower part of the dividend shifted in the upper bit direction is stored. Quotient And a second data holding means for holding a quotient at the end of the processing, and shifting the value held by the second data holding means by one bit in the upper bit direction or transferring the result as it is, and The second shift means for storing the data in the second data holding means again, and the counting means therein, and when the counting means indicates the start of the processing, the dividend and the divisor are the same. If the sign indicates a subtraction, if the sign is a different sign, an addition is indicated, and if the counting means indicates that the processing is from the start to the end, the value of the least significant bit of the second data holding means is 0. If the value indicates the end of the process, and if the value of the least significant bit of the second data holding means is 0, the instruction indicates addition. No. When the transfer of an input is instructed and the counting means indicates to the first shift means that the processing is not the end or the immediately preceding processing, a one-bit shift in the upper bit direction is instructed. When indicating the end of the process or the process immediately before, the transfer is instructed, and for the second shift means,
When the counting means indicates that the processing is not completed,
Control means for instructing a one-bit shift in a higher-order bit direction to insert a carry or its inverted value in the least significant bit in the arithmetic means, and instructing transfer when the counting means indicates the end of processing, The value held in the data holding means and the value held in the divisor holding means are respectively stored in the first
And the second input, the value to be inserted into the least significant bit of the first shift means is the shift overflow from the most significant bit in the second shift means, and the bit to be inserted into the second shift means in the control means. The instruction regarding the sign of the divisor is negative and any of the bits of the first data holding means in the current and previous processing or the least significant bit of the second data holding means has already been output by the second shift means. When any of the bits except for all of the values inserted in is 1, the carry in the arithmetic means is inverted, otherwise, the carry in the arithmetic means is used. , Between the start and end of the process,
Calculating the quotient and the remainder by repeating the operation in the arithmetic means and the shift in the first shift means and the second shift means a number of times equal to the difference between the number of bits of the dividend and the number of bits of the divisor. To divide. 12. A divisor holding means for holding a divisor of a signed number, adding the first and second inputs and outputting the result, or outputting the result from the first input to the second input. Calculating means for performing the subtraction and outputting the result or transferring and outputting the first input as it is; first shifting means for shifting the output of the calculating means by one bit in the upper bit direction or transferring the output as it is; At the start of the division process, the upper part of the word length equal to the word length of the divisor holding unit of the dividend of the signed number is held, and during the execution of the process, the output of the first shift unit is held. At the end, first data holding means for holding a remainder, at the start of processing, the remaining lower part of the dividend is held, and during the processing, the lower part of the dividend shifted in the upper bit direction is stored. Hold A second data holding means for holding 0 at the end of the processing, a third data holding means for holding a part of the quotient during the execution of the processing and holding the quotient at the end of the processing, The value held in the second data holding means is shifted by one bit in the upper bit direction by inserting it into bits, or the value held in the second data holding means is transferred as it is, and the result is returned to the second data holding means. A second shifting means for storing in the holding means; and a second means for shifting the value held in the third data holding means by one bit in the upper bit direction or transferring the value as it is and storing the result in the third data holding means again. A three-shift means, and a counting means therein, and for the arithmetic means, when the counting means indicates the start of processing, if the dividend and the divisor have the same sign, the subtraction is instructed. If the value of the least significant bit of the third data holding means is 0, the addition is instructed, and if the value of the least significant bit of the third data holding means is 0, the addition is instructed. When the subtraction is instructed and the counting means indicates the end of the processing, if the value of the least significant bit of the third data holding means is 0, the addition is instructed, while if the value is 1, the transfer of the first input is instructed. When the counting means indicates that the processing is not the end of the processing or the processing immediately before, the first shifting means instructs the first shifting means to shift one bit in the upper bit direction. When indicated, a transfer is instructed, and for the second shift means,
When the counting means indicates that the processing is not completed,
When the counting means indicates the end of the processing, the transfer is instructed. When the counting means indicates the end of the processing, the counting means indicates the end of the processing. O a carry in the arithmetic means
And instructs the 1-bit shift of the upper bit direction of inserting the inverted value to the least significant bit, when the counting means indicate the end of the processing and control means for instructing forward, held in the first data holding means The obtained value and the value held in the divisor holding means are respectively stored in the first
And the second input, the value to be inserted into the least significant bit of the first shift means is the shift overflow from the most significant bit in the second shift means, and the bit to be inserted into the third shift means in the control means. The instruction regarding the divisor is negative, and any bit of the first data holding unit or any bit of the second data holding unit in the current or previous processing is 1
In the case of, carry carry inversion in the arithmetic means,
At other times, the carry in the arithmetic means is used, and based on the count by the counting means, between the start and the end of the processing, the arithmetic in the arithmetic means and the first shift means and the second shift means and A dividing apparatus characterized in that a quotient and a remainder are obtained by repeating the shift in the third shift means a number of times equal to the difference between the number of bits of the dividend and the number of bits of the divisor. 13. At the start of the processing, the dividend of the signed number is divided into an upper part of the word length equal to the word length of the divisor of the signed number and the remaining lower part, each of which is a first value or a second value. An initial setting step of storing the value as a value; a counting step of counting the number of repetition processes; and a start of the process being indicated by the counting step, if the dividend and the divisor have the same sign, the divisor from the first value. If the sign is a different sign, the first value and the divisor are added. When the counting step indicates that the processing is from the start to the end, the least significant bit of the second value is set to 0. If the first value and the divisor are added, the divisor is subtracted from the first value if 1, and the end of the processing is indicated by the counting step, and the dividend and the divisor have the same sign. If the least significant bit of the second value is 0, the first value and the divisor are added, and the end of the process is indicated by the counting step, and when the dividend and the divisor have different signs, the second value is used. If the least significant bit of the value is 1, the arithmetic step of subtracting the divisor from the first value, and when the counting step indicates that the processing is not the end of the processing or the processing immediately before the end, the last shift in the second shifting step A first shift step of inserting a shift overflow from the upper bit into the least significant bit and shifting the value obtained in the operation step by one bit in the direction of the upper bit to make the shift result a new first value; When the counting step indicates that the processing is not completed, the carry in the calculation step or its inverted value is inserted into the least significant bit, and the A second shift step of shifting the value of by 1 bit in the upper bit direction and setting the shift result as a new second value, and a quotient correction step of adding 1 to the second value. In the second shift step, when the value to be inserted in the least significant bit in the counting step indicates the start of the processing, if the sign of the divisor is negative, the carry in the arithmetic step is inverted. If the carry is a step, and the counting step indicates that processing is not started, the dividend is positive and the divisor is negative, or the dividend is negative and the divisor is positive and the current or previous processing is performed. Of all bits of the first value and bits of the second value other than those inserted into the least significant bit by the immediately preceding step. If the shift is also 0 or the dividend is negative and the divisor is negative and the last step of any one of the bits of the first value or the second value in the current and previous processing, If any of the bits in the portion except for the bits inserted are 1, the carry in the operation step is inverted, otherwise, the carry in the operation step is used. From the start to the end of the process, repeat the operation step and the first shift step and the second shift step the number of times equal to the difference between the number of bits of the dividend and the number of bits of the divisor,
The obtained first value is a remainder, and the quotient correction step is performed when the dividend and the divisor have different signs, and when the dividend has the same sign, the second value obtained without performing the quotient correction step is a quotient. A division method characterized by: 14. At the start of processing, the dividend of the signed number is divided into an upper part of the word length equal to the word length of the divisor of the signed number and the remaining lower part, each of which is a first value or a second value. An initial setting step of holding as a value, a counting step of counting the number of repetitive processes, and when the counting step indicates the start of processing, if the dividend and the divisor have the same sign, the divisor from the first value If the sign is a different sign, the first value and the divisor are added, and when the counting step indicates that the processing is from the start to the end, if the least significant bit of the third value is 0, For example, if the first value and the divisor are added, and if 1, the subtractor subtracts the divisor from the first value, the counting step indicates the end of processing, and the dividend and the divisor have the same sign. If the least significant bit of the second value is 0, the first value and the divisor are added, and the end of the process is indicated by the counting step, and when the dividend and the divisor have different signs, the second value is used. If the least significant bit of the value is 1, the arithmetic step of subtracting the divisor from the first value, and if the counting step indicates that the processing is not the end of the processing or the processing immediately before it, the most significant bit in the second shifting step A first shift step of inserting a shift overflow from a bit into a least significant bit, shifting the value obtained in the operation step by one bit in the direction of a higher bit, and setting the shift result as a new first value; When the counting step indicates that the processing is not completed, 0 is inserted into the least significant bit, and the second value is shifted by one bit toward the upper bit. A second shift step in which the result of the shift is a new second value, and when the counting step indicates that the processing is not completed, the carry in the operation step or its inverted value is inserted into the least significant bit. A third shift step of shifting the third value by one bit in the direction of the higher-order bit to make the shift result a new third value; and a quotient correction step of adding 1 to the third value. When the start of the process is indicated by the counting step, the value to be inserted into the least significant bit in the third shift step is set to the inversion of the carry in the calculation step if the sign of the divisor is negative. Then, the carry in the calculation step is performed. When the counting step indicates that the processing is not started, the dividend is positive and the previous When the divisor is negative, or when the dividend is negative, the divisor is positive, and all bits of the first value and all bits of the second value in the current or previous processing are both 0. Alternatively, if the dividend is negative, the divisor is negative, and any one of the bits of the first value or any one of the second values in the current and previous processing is 1, Carry inversion, otherwise, carry in the calculation step, based on the count in the counting step, from the start to the end of the processing, the calculation step and the first shift step and the The second shift step and the third shift step are repeated a number of times equal to the difference between the number of bits of the dividend and the number of bits of the divisor, and the obtained first value is a remainder. When the dividend and the divisor have different signs, the quotient correction step is performed. When the dividend has the same sign, the third value obtained without performing the quotient correction step is used as a quotient. Method. 15. A divisor holding means for holding a divisor of a signed number, adding the first and second inputs and outputting the result, or outputting the result from the first input to the second input. Calculating means for performing the subtraction and outputting the result or transferring and outputting the first input as it is; first shifting means for shifting the output of the calculating means by one bit in the upper bit direction or transferring the output as it is; At the start of the division process, the upper part of the word length equal to the word length of the divisor holding unit of the dividend of the signed number is held, and during the execution of the process, the output of the first shift unit is held. At the end, the first data holding means for holding the remainder; At the start of the processing, the remaining lower part of the dividend is held, and during the processing, the lower part of the dividend shifted in the upper bit direction is stored. Quotient And a second data holding means for holding a quotient at the end of the processing, and shifting the value held by the second data holding means by one bit in the upper bit direction or transferring the result as it is, and The second shift means for storing the data in the second data holding means again, and the counting means therein, and when the counting means indicates the start of the processing, the dividend and the divisor are the same. If the sign indicates a subtraction, if the sign is a different sign, an addition is indicated, and if the counting means indicates that the processing is from the start to the end, the value of the least significant bit of the second data holding means is 0. If the value is 1, the subtraction is instructed. If the counting means indicates the end of the processing and the dividend and the divisor have the same sign, the value of the least significant bit of the second data holding means is If the instruction is 1, the transfer of the first input is instructed. If the counting means indicates the end of the processing, and the dividend and the divisor have different signs, the least significant bit of the second data holding means. If the value of the bit is 0, it indicates the transfer of the first input, while if it is 1, it indicates the subtraction. When indicated, a one in the high order bit direction
When the bit shift is instructed and the counting means indicates the end of the processing or the processing immediately before it, a transfer is instructed, and the second shifting means is informed that the counting means is not the end of the processing. Control means for instructing a one-bit shift in the upper bit direction to insert a carry or its inverted value in the least significant bit in the arithmetic means, and instructing transfer when the counting means indicates the end of processing, Quotient correcting means for adding 1 to the value held in the second data holding means, wherein the value held in the first data holding means and the value held in the divisor holding means are respectively stored in the first of the arithmetic means.
And the second input, the value to be inserted into the least significant bit of the first shift means is the shift overflow from the most significant bit in the second shift means, and the bit to be inserted into the second shift means in the control means. When the counting means indicates the start of the processing, if the sign of the divisor is negative, the carry in the calculating means is inverted, while if the sign is positive, the carry in the calculating means is performed. When the dividend is positive and the divisor is negative, or when the dividend is negative and the divisor is positive and all bits of the first data holding means in the current or previous processing and Bits of the second data holding unit other than all the values already inserted in the least significant bit by the second shift unit are bits. If both are 0 or the dividend is negative and the divisor is negative and any one of the bits of the first data holding means or the second shift of the second data holding means in the current and previous processing, If any one of the bits except for all of the values inserted in the least significant bit by the means is 1, the carry in the arithmetic means is inverted, otherwise, the carry in the arithmetic means is used, On the basis of the counting by the counting means, between the start and the end of the processing, the calculation in the calculation means and the shift in the first shift means and the second shift means are performed by the number of bits of the dividend and the number of bits of the divisor. Repeat the number of times equal to the difference, the value held in the first data holding means as a remainder, when the dividend and the divisor have different signs The quotient correction unit adds 1 to the value held in the second data holding unit, but does not perform any operation when the value is the same, and the value held in the second data holding unit is used as the quotient. A dividing device. 16. A divisor holding means for holding a divisor of a signed number, adding the first and second inputs and outputting the result, or outputting the result of the addition from the first input to the second input. Calculating means for performing the subtraction and outputting the result or transferring and outputting the first input as it is; first shifting means for shifting the output of the calculating means by one bit in the upper bit direction or transferring the output as it is; At the start of the division process, the upper part of the word length equal to the word length of the divisor holding unit of the dividend of the signed number is held, and during the execution of the process, the output of the first shift unit is held. At the end, first data holding means for holding a remainder, at the start of processing, the remaining lower part of the dividend is held, and during the processing, the lower part of the dividend shifted in the upper bit direction is stored. Hold A second data holding means for holding 0 at the end of the processing, a third data holding means for holding a part of the quotient during the execution of the processing and holding the quotient at the end of the processing, The value held in the second data holding means is shifted by one bit in the upper bit direction by inserting it into bits, or the value held in the second data holding means is transferred as it is, and the result is returned to the second data holding means. A second shifting means for storing in the holding means; and a second means for shifting the value held in the third data holding means by one bit in the upper bit direction or transferring the value as it is and storing the result in the third data holding means again. A three-shift means, and a counting means therein, and for the arithmetic means, when the counting means indicates the start of processing, if the dividend and the divisor have the same sign, the subtraction is instructed. If the value of the least significant bit of the third data holding means is 0, the addition is instructed, and if the value of the least significant bit of the third data holding means is 0, the addition is instructed. If the counting means indicates the end of the process and the dividend and the divisor have the same sign, if the value of the least significant bit of the third data holding means is 0, then the addition means 1 Then, transfer of the first input is instructed, and when the counting means indicates the end of the process and the dividend and the divisor have different signs, if the value of the least significant bit of the third data holding means is 0, the second data is transferred. Instructs transfer of one input while instructs subtraction if it is one, and instructs the first shift means to terminate the processing or to indicate that the processing is not immediately preceding by the counting means. Of 1
When the bit shift is instructed and the counting means indicates the end of the processing or the processing immediately before it, a transfer is instructed, and the second shifting means is informed that the counting means is not the end of the processing. When it indicates, it instructs a one-bit shift in the upper bit direction, when the counting means indicates the end of processing, instructs transfer, and instructs the third shift means that the counting means does not end processing. Control means for instructing a one-bit shift in the upper bit direction to insert a carry or its inverted value in the least significant bit in the arithmetic means, and instructing transfer when the counting means indicates the end of processing, Quotient correction means for adding 1 to the value held in the third data holding means, wherein the value held in the first data holding means and the value held in the divisor holding means are provided. First respectively the arithmetic means
And the second input, the value to be inserted into the least significant bit of the first shift means is the shift overflow from the most significant bit in the second shift means, and the bit to be inserted into the third shift means in the control means. When the counting means indicates the start of the processing, if the sign of the divisor is negative, the carry in the calculating means is inverted, while if the sign is positive, the carry in the calculating means is performed. When the dividend is positive and the divisor is negative, or when the dividend is negative and the divisor is positive and all bits of the first data holding means in the current or previous processing and When all the bits of the second data holding means are 0 or the dividend is negative, the divisor is negative, and the current and previous processing is performed. If any of the bits of the first data holding means or any of the bits of the second data holding means are 1, the carry in the arithmetic means is inverted; otherwise, the carry in the arithmetic means is reversed. When the sign of the divisor is negative and any bit of the first data holding means or any bit of the second data holding means is 1, the carry in the arithmetic means is inverted, Time is a carry in the calculating means, and based on the count by the counting means,
Between the start and the end of the processing, the calculation in the calculation means and the shift in the first shift means and the second shift means and the third shift means are performed by using the number of bits of the dividend and the number of bits of the divisor. Repeat the number of times equal to the difference, the remainder held in the first data holding means as a remainder, when the dividend and the divisor are different signs, the quotient correction means to hold the third data holding means A dividing device configured to add 1 to a stored value and do nothing at the same sign, and use the value held in the third data holding means as a quotient.