JP2605848B2 - Non-restoring divider - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-restoring divider capable of performing signed division at high speed by providing a register that can set and reset one bit. .

2. Description of the Related Art FIG. 2 is a block diagram of a conventional non-restoring divider. In FIG. 2, 1 is an n-bit register (SR
H), 2 is an m-bit register (SRL), 3 is an n-bit register (DR), and 4 is an adder / subtractor for adding or subtracting DR3 to SRH1.

Non-restoring division does not require addition for restoration,
Instead, it is necessary to switch the operation in each row to addition and subtraction depending on whether the sign of the adder / subtractor output in the previous row matches the sign of the dividend. That is, when the sign of the partial remainder is opposite to the dividend due to the failed subtraction, the quotient must be “0” and the divisor must be added in the next row. When the sign of the partial remainder is not inverted, the quotient must be set to 1 and the next row must be subtracted.

 Table 1 shows a calculation example.

When the divisor is shifted to the right (ie, halved) when the trial operation fails, the same result is obtained as when the divisor is subtracted from the beginning without trial operation. . In other words, the same result as in the case where the divisor is shifted to the right (1/2 of the divisor) and subtracted after recovering the partial remainder by adding again in the recovery type binary division is obtained. Table 2 shows this correspondence.

That is, the operation of dividing an unsigned binary number in FIG. 2 is as follows. “0” is initially assigned to SRH1 and SR
L2 is assigned a positive dividend S, and DR3 is assigned a positive divisor D. Next, SRH1 and SRL2 are shifted left by one bit,
After that, DR3 is subtracted from SRH1, and the result is returned to SRH1.
Also, if the partial remainder at that time, that is, the output of the adder / subtractor is negative, “0” is determined as a subtraction failure, and “1” otherwise.
Substitute for the least significant bit of SRL2.

Next, SRH1 and SRL2 are shifted one bit to the left, and addition / subtraction is performed based on the previous addition / subtraction result.
Return to Also, depending on the sign of the partial remainder, “1” or “0” is converted to SR
Assign to the least significant bit of L2. Then, this is repeated m times in total.

Then, the quotient remains in SRL2 and the remainder remains in SRH1. However, since the remainder can be negative, if the result is negative, the last subtraction has failed and the remainder must be recovered, that is, the divisor D must be added.

SUMMARY OF THE INVENTION However, in the above-described conventional configuration, only a positive number can be handled, and in the case of a negative number, calculation is performed after correcting the value once, and after the calculation, the quotient is returned to negative again if necessary. Operation is required.

The present invention solves the above-mentioned conventional problems, and provides a non-restoring divider that can perform division by the same algorithm even when the dividend is negative by providing a register that can set and reset 1 bit. It is intended to be.

Means for Solving the Problems In order to achieve this object, a non-restoring divider according to the present invention provides a method for determining whether a partial remainder is "0" when an operation result in each row is "0". Set and reset when the least significant bit in each row of the dividend enters "1"
It has a bit register and uses the result of this register to correct the quotient.

Operation With this configuration, even when the dividend or the divisor is negative, the quotient can be easily corrected.
Alternatively, the division can be performed without replacing the divisor with a positive number.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a non-restoring divider according to an embodiment of the present invention.
5 indicates that the output (ZFLG) is “1” when the result of addition / subtraction is “0”, and that the ZFLG is “0” when “1” is input to the least significant bit of SRH1 when shifting SRH1 and SRL2. Is a register.

The division of a signed number taking a two's complement representation is realized by extending the above-described conventional algorithm for an unsigned number.

First, when the dividend is positive and the divisor is positive, the calculation is performed in the same manner as in the related art.

Next, the case where the dividend is positive and the divisor is negative is realized by inverting the addition and subtraction with respect to the operation when the dividend is positive and the divisor is positive. That is, the division of (positive number) ÷ (negative number) is replaced with the operation of (positive number) ÷ (positive number). Therefore, the sign of the obtained quotient is inverted as compared with the original quotient. Therefore, a correction for inverting the sign of the quotient, that is, a correction for inverting the bit and adding 1 is required.

The remainder is obtained in the same manner as when the dividend is positive and the divisor is positive. However, when the remainder is less than 0, the divisor is negative, so that when the divisor is positive, a correction in which the sign is inverted, that is, a correction in which the divisor is subtracted from the remainder to make the remainder 0 or more is necessary.

Next, a case where the dividend is negative and the divisor is positive will be described.

When the dividend is negative, the calculation is basically performed in the same manner as when the dividend is positive, and the quotient and remainder are corrected later.

Originally, the non-restoring division method is based on the assumption that the dividend is positive, and therefore cannot cope with the case where the dividend is negative.

That is, the essential idea of the non-restoring division method is
If the divisor is too much subtracted from the dividend, add
On the other hand, if the addition is excessive, the quotient and the remainder are obtained by performing the subtraction in the next step. On the other hand, according to the arithmetic method adopted in the present invention, the non-restoring division method performs subtraction when the partial remainder is positive, regardless of whether the dividend is positive or negative, and it is negative. In this case, add. For this reason, when the dividend is negative, it is determined in reverse whether the subtraction is too large or too large in the case where the dividend is positive, and the addition and the subtraction are performed in reverse.

Therefore, when the dividend is negative and the divisor is positive, the quotient obtained by the above operation is equal to a bit-reversed quotient when the dividend is positive and the divisor is positive.

However, when the dividend is negative and the divisor is positive, the quotient when the dividend is positive and the divisor is positive must be obtained by sign-inverting, that is, bit-inverting, the quotient when the dividend is positive and adding one. Therefore, the fact that a quotient obtained only by bit inversion by the above operation is obtained means that one less quotient than the original quotient is obtained.

Therefore, when the dividend is negative and the divisor is positive, it is necessary to add one to the obtained quotient.

It should be noted here that when the partial remainder is “0” and all data input when the shift is “0”, that is, when the remainder is divisible without any remainder, and when the dividend is negative even though it is negative Is obtained by simply inverting the sign of the quotient of.

Referring to FIG. 4, “−6−3”, that is, “(11010) ₂ ÷
(011) This will be described by taking ₂ as an example.

As shown in FIG. 4A, the quotient (110) ₂ and the remainder (101) ₂
However, the quotient “1” of the second bit from the lower order becomes a problem. In other words, this quotient “1” is based on the determination of the partial remainder “000”. However, as described above, in order to perform the division completely opposite to the case where the dividend is positive and the divisor is negative, , The partial remainder "000" is determined to be negative, a quotient "0" is obtained, and addition must be performed in the next stage.

However, since “000” is a positive number in the two's complement, even if the partial remainder is “000”, it is determined to be a positive number and subtracted. Therefore, the third partial remainder becomes "000", and the quotient of the first bit from the lower order becomes "0".

Accordingly, in comparison with the quotient (010) ₂ of “6 ÷ 3” where the dividend is positive and the divisor is positive shown in FIG. 4B, “−6 ÷ 3”
In this case, a quotient (110) ₂ in which the bit is inverted and 1 is added, that is, a quotient whose sign is simply inverted is obtained.

As described above, when the dividend is negative, the divisor is positive, the partial remainder is “0”, and all the data input when the shift is “0”, the dividend is one more than when the dividend is not divisible by the divisor. Is obtained as a quotient. That is, a quotient that does not require correction is obtained. Therefore, when it is detected that the partial remainder is “0” and all the data input when the shift is “0”, the quotient is not corrected.

Note that the dividend is always divisible by the divisor if the partial remainder is “0” and all the input data is “0” when shifting, but even if the dividend is divisible by the divisor, the partial remainder is “0” and All data input during the shift may not be "0".

Also, the remainder needs to be corrected in substantially the same manner as when the dividend is positive and the divisor is positive.

Specifically, the remainder must be negative because the dividend is negative, so that when the remainder is 0 or more, it is necessary to perform correction. Therefore, in this case, the sign of the remainder is corrected when the dividend is positive and the divisor is positive, that is, the subtraction is performed on the remainder. When the remainder is 0 or more, there is no need to perform correction.

However, if the partial remainder is “0” and all the input data is “0” when the shift is performed, it means that the dividend is divisible by the divisor, so that the remainder is corrected to “0”.

Next, a case where the dividend is negative and the divisor is negative will be described.

In this case, the operation is basically performed in the same manner as when the dividend is positive and the divisor is negative.

Therefore, as in the case where the dividend is negative and the divisor is positive,
A quotient is obtained by bit-inverting the quotient when the dividend is positive and the divisor is negative. Here, the quotient when the divisor is negative is obtained by inverting the sign of the quotient when the divisor is positive, so that a quotient obtained by adding one to the original quotient is obtained.

Therefore, when the dividend is negative and the divisor is negative, it is necessary to perform a bit inversion of the obtained quotient.

However, when the partial remainder is “0” and all data input is “0” when shifted, one is added to the quotient when the dividend is not divisible by the divisor, as in the case where the dividend is negative and the divisor is positive. Things are obtained as quotients. Therefore, it is necessary to perform the same correction as when the dividend is negative and the divisor is positive.

Also, the remainder needs to be corrected in substantially the same manner as when the dividend is positive and the divisor is negative.

More specifically, since the dividend is negative as in the case where the dividend is negative and the divisor is positive, the remainder must be negative. Therefore, when the remainder is 0 or more, it is necessary to perform correction. Therefore, in this case, the correction in which the sign is inverted with respect to the remaining correction when the dividend is positive and the divisor is negative, that is, correction for adding the divisor extra is performed. When the remainder is 0 or more, there is no need to perform correction.

However, if the partial remainder is “0” and all the input data is “0” when the shift is performed, it means that the dividend is divisible by the divisor, so that the remainder is corrected to “0”.

FIG. 3 shows an 8-bit dividend (11011010) ₂ = (− 38).
₁₀ shows a calculation flowchart of an example in which ₁₀ is divided by a 4-bit divisor (1101) ₂ = (− 3) ₁₀ . The dividend is SRL2 (m =
8), SRL2 is sign-extended to SRH1 (n = 5), and (11111) ₂ is entered. The divisor is sign-extended (1110
1) Enter ₂ .

First, a left shift is performed, and (11111) ₂ enters SRH1. At this time, since the least significant bit is "1", ZFLG is reset. Next, subtraction is performed assuming that the initial q is “0”. Here, the result of subtraction (00010) ₂
G remains retained. Next, the left shift is performed again, and (00101) ₂ is entered in SRH1. At this time, the least significant bit is “1” as described above, and thus the ZFLG is reset.
However, the value is the same as not actually changing. Then perform the addition because there was a q ₀ is "1". Here, since the result of the addition is (00010) ₂ , the ZFLG is held. Hereinafter, the same process is repeated until the quotient (11110011) ₂ and the remainder (00
01) Get ₂ . Here, the correspondence of addition and subtraction and the correction of the quotient are the third.
It is shown in the table.

From Table 3 above, the quotient is negative for the dividend, negative for the divisor, and ZFLG
Is “0”, the bit may be inverted. For the remainder, the remainder + divisor may be obtained. Then, quotient (00001100)
₂ = 12, remainder (0001) ₂ + (1101) ₂ = (1110) ₂ = -2
Get. This is consistent with the answer of (−38) ÷ (−3) = 12... (−2).

Now, based on the logic shown in Table 3, each control signal is simple.

The initial q signal may be obtained by inverting the sign bit of the dividend. The addition and subtraction are controlled by the sign bit of the divisor and the q signal. ZFLG is as described above, and the remaining sign can be determined by the remaining sign bit.

When the dividend is "0", when the quotient is obtained by the above-described procedure, it is conceivable that the ZFLG is not set and reset once, and the value remains at the initial value. In this case, the quotient is correct whether the initial value is set or reset, but by setting the initial value of ZFLG to "1", the dividend is negative in the remainder correction and ZFLG = When the dividend is "1", there is no problem even if the dividend is corrected even when the dividend is positive, so that the circuit can be reduced. In addition, since an uncertain signal is not left in a simulation or the like, a burden when studying a circuit can be reduced.

According to the present invention, by providing a 1-bit register that can be set and reset, when the dividend or the divisor is negative, it is possible to omit the process of once replacing it with a positive number and dividing. It is possible to realize an excellent non-restoring type divider which can obtain the quotient with high speed and with a constant algorithm independent of the sign.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a non-restoring divider according to one embodiment of the present invention, FIG. 2 is a block diagram of a conventional non-restoring divider, FIG.
FIG. 4 is a flowchart for calculating 8 bits ÷ 4 bits, and FIG. 4 is a flowchart of division when the dividend is negative and the divisor is positive, and when the dividend is positive and the divisor is positive. 1... N-bit register (SRH), 2... M-bit register (SRL), 3... N-bit register (DR),
4... Add / subtractor, 5... 1-bit set reset, possible register (ZFLG).

Claims (1)

(57) [Claims] 1. A register which is set when a partial remainder is "0", and is reset when input data is "1" when the partial remainder is shifted, wherein a dividend is positive and a divisor is positive , The quotient is not corrected, and the remainder is not corrected when the remainder is 0 or more,
When the remainder is less than 0, the divisor is added to the remainder, and when the dividend is positive and the divisor is negative, the quotient is bit-inverted and added to the quotient. When the remainder is less than 0, and when the remainder is less than 0, the divisor is subtracted from the remainder. When the data of the register is “0”, the dividend is negative and the divisor is positive, In addition to the correction of adding 1 to the quotient, when the remainder is 0 or more, the divisor is subtracted from the remainder. When the remainder is less than 0, the remainder is not corrected. If the dividend is “1”, the dividend is negative and the divisor is positive, the quotient is not corrected, and the remainder is corrected to “0”. The register data is “0”, the dividend is negative and the divisor is negative. , When the quotient is corrected by inverting the bit and the remainder is 0 or more The remainder is corrected by adding a divisor. When the remainder is less than 0, the remainder is not corrected. On the other hand, when the data of the register is “1”, the dividend is negative and the divisor is negative, the quotient is A non-restoring divider which performs a correction for inverting a bit and adding 1 and a correction for setting the remainder to "0".