JP3284717B2 - Barrel shifter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for executing data shift processing. More specifically, the present invention relates to an apparatus for performing a shift processing of a data tone which is to be handled by a data tone which is higher than the data tone. The present invention relates to a barrel shifter that performs a shift process at high speed by performing a shift process.

[0002]

2. Description of the Related Art In a processor used for signal processing, image processing, or the like, a barrel shifter is used to perform data digit alignment and bit alignment at high speed.

In these conventional barrel shifters, when the effective bit length of data is 2 ⁿ , a shift control register for indicating the number of shift bits prepares a bit length of n + 1 bits, and 2 ⁿ −1 bit left shift and 2 ⁿ Controls bit shift right.

However, when floating point data is handled by a fixed point arithmetic unit, for example, when multiplication between data having an effective bit length of 2 ⁿ is performed, multiplication between data having an exponent of 2 ⁿ is performed. In this case, the exponent part of the multiplication result is an addition of the exponent parts, and becomes 2 ^{n + 1} , which cannot be reduced by a barrel shifter using a shift control register having a bit length of n + 1 bits. Normally, in this case, it is determined by software whether or not the number of shift bits fits into the bit length of the shift control register. If the number of shift bits does not fit, correction of output data (conversion to all 0s and all 1s) is performed. Therefore, an extra step is required for the determination, and the execution speed is reduced.

Therefore, there is a method of performing processing by hardware in order to speed up the processing. FIG. 3 is a block diagram of a conventional barrel shifter (eg, logic design by LSI, pp. 46-48, author: Satoshi Okukawa, Kyoritsu Shuppan Co., Ltd.)
It is shown. In the figure, reference numeral 1 denotes input data to be shifted, 11 to 14, 32, and 33 correspond to each bit of an enable signal 4 to be described later with respect to the input data 1, and are 1 bit to the right, 2 bits, and 4 bits, respectively. bit,
1-bit right shifter, 2-bit right shifter, 4-bit right shifter, 8-bit right shifter, 16-bit right shifter for shifting 8 bits, 16 bits, and shifting left 32 bits
32-bit left shifter, 5 is an externally applied shift number, 8 is an externally applied shift number write signal, 31
Stores the number of shift bits 5 in synchronization with the shift number write signal 8 from the outside, and shifters 11 to 14, 32 and 33
6-bit shift control register that outputs the enable signal 4 to the first and second bits, the bits 0 to 5 each being a 1-bit right shifter 11, a 2-bit right shifter 12, and a 4-bit right shifter 1.
3, 8-bit right shifter 14, 16-bit right shifter 32,
An enable signal 3 corresponding to the 32-bit left shifter 33 and controlling the shift is the final output data of the 32-bit left shifter.

In the conventional barrel shifter constructed as described above, the shift number 5 is changed from the shift number write signal 8
The right shifters 11 to 14 and 32 and the left shifter 33 shift according to the values of bits 0 to 5 of the enable signal 4 stored in the shift control register 31 and output, and output the output data 3.

[0007]

However, in such a conventional barrel shifter, when the effective bit length of the data is originally 2 ⁿ , the bit length of the shift control register indicating the number of shift bits is n + 1 bits, and the shifter is also n + 1 bits.
Although it is sufficient to prepare a shifter of stages, there is a problem that one extra stage is required, the circuit scale is increased, and the processing speed is reduced by the increase of one stage of shifters.

The present invention solves such a conventional problem. By adding hardware having a relatively small circuit size, the configuration of the barrel shifter when the effective bit length is set to 2 ⁿ is reduced to one. It can be composed of n + 1 stages with reduced stages,
The purpose of the present invention is to perform high-speed shift processing.

[0009]

In order to achieve the above object, a barrel shifter according to the present invention synchronizes input data with an effective bit length of 2 ⁿ bits, where n is a natural number, and the number of shift bits in synchronization with an external control signal. An n + 2 bit shift control register to be stored, two bits of a bit n + 1 and a bit n out of the n + 2 outputs of the shift control register, an arithmetic / logic shift signal for instructing an externally applied arithmetic / logic shift, and the input A shift control circuit that receives the most significant bit of data as an input and outputs an all 0 generation signal, an all 1 generation signal, and a left shift enable signal instructing a left shift of 2 ⁿ bits, and n + 2 outputs of the shift control register Of which
The input data based on n lower bits, 2 ⁰ bit,
2 ¹ bit, ..., and right shifter n stages performing 2 ^n-bit right shift, all 0 the a output of the shift control circuit
The output of the n-stage right shifter is shifted to all 0 data, all 1 data, or left 16 bits based on the generated signal, the all 1 generated signal, and the left shift enable signal instructing 2 ⁿ bit left shift. And a left shifter for outputting the converted data.

[0010]

According to the present invention, the upper two bits of the shift control register, the most significant bit of the input data, and the externally applied arithmetic logic shift signal enable all 0 data at the final stage (n + 1 stage) of the shifter. , Or all 1 data, or by outputting data shifted left by 16 bits with respect to the input data, a shift process equivalent to the conventional barrel shifter of FIG. 3 can be performed at high speed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A barrel shifter according to one embodiment of the present invention will be described.
This will be described with reference to the drawings.

FIG. 1 is a block diagram showing a barrel shifter according to an embodiment (n = 4) of the present invention. 1 is input data, 2 is an enable signal from a shift control circuit 16 described later, 3 is output data, 5 is the number of shifts, 6 is the MSB of input data, 7 is an arithmetic shift signal, 8 is a shift number write signal, and 11 is a shift number write signal. 1-bit right shifter, 12 is a 2-bit right shifter, 13 is a 4-bit right shifter, 14 is an 8-bit right shifter, 15 is a 16-bit left shifter having a function of correcting output data. ing. Reference numeral 16 denotes a shift control circuit described later.

FIG. 2 shows details of the shift control circuit 16. 31 is a barrel shifter control register, 21 is O
R gates 22, 23, 24, 25 and 26 are AND
Gates 27, 28, 29 and 30 are NOT gates. Bits 5 and 4 of the barrel shifter control register 31, the input data MSB6, and the arithmetic shift signal 7
As shown in the figure, bits 5 to 0 of the barrel shifter control register, the output signal of the OR gate 21 and the output signal of the AND gate 24 are connected to the barrel group as the enable signal 2 of the barrel shifter section. Connected to the unit.

The operation of the barrel shifter device configured as described above will be described with reference to FIGS.

First, in the shift control circuit of FIG. 2, the effective bit length of input data is set to 16 bits. A positive number is set in the barrel shift control register 31 when performing a left shift, and a negative number (two's complement) is set when performing a right shift.

In the barrel shifter control register 31,
When the left shift overflows, that is, when bit 5 is 0 and bit 4 is 1, an output data 0 correction signal is output.

When the right shift overflows, that is, when bit 5 is 1 and bit 4 is 0, when the MSB of the input data is 0, or when the MSB of the input data is 1 and a logical shift is performed (the arithmetic shift signal is 0) Time) is output data 0
A correction signal is output.

At the time of right shift overflow, an output data 1 correction signal is output when the MSB of the input data is 1 and the arithmetic shift is performed (when the arithmetic shift signal is 1).

At this time, the 16-bit left shifter at the final stage in the barrel shifter device of FIG. 1 corrects all the bits of the output data to 0 by the output data 0 correction signal, and outputs all the output data by the output data 1 correction signal. Correct the bit to one.

As described above, according to the present invention, the 16-bit input data 1 and the 6-bit shift control register 31 for storing the shift number 5 in synchronization with the shift number write signal 8.
And two of bit 6 and bit 4 of the six outputs of the shift control register 31, an arithmetic and logical shift signal 7 for instructing arithmetic and logical shifts given from the outside, and the MSB6 of the input data as inputs. , A shift control circuit 16 for outputting an all 0 generation signal, an all 1 generation signal, an enable signal 2 including a left shift enable signal for instructing a 16-bit left shift, and an output 6 of the shift control register 31.
Four-stage right shifters 11 to 15 for right-shifting input data 1 by 1 bit, 2 bits, 4 bits and 8 bits based on the lower 4 bits of the book;
6 based on an enable signal 2 including an all 0 generation signal, an all 1 generation signal, and a left shift enable signal for instructing a left shift of 16 bits, , Or all 1 data,
Alternatively, by including the left shifter 15 that outputs data shifted by 16 bits to the left, it is possible to detect an overflow of the shift data, correct the data, and execute the shift processing at high speed.

[0021]

As described above, according to the present invention, it is possible to detect an overflow of shift data and correct the data without adding large hardware, and to execute the shift processing at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a barrel shifter according to an embodiment of the present invention.

FIG. 2 is a block diagram of the shift control circuit.

FIG. 3 is a block diagram of a conventional barrel shifter device.

[Explanation of symbols]

 Reference Signs List 1 input data 2 enable signal from shift control circuit 3 output data 5 shift number 6 input data MSB 7 arithmetic shift signal 8 shift number write signal 11 1-bit right shifter 12 2-bit right shifter 13 4-bit right shifter 14 8-bit right shifter 15 16-bit left shifter 16 shift control circuit 21 OR gate 22, 23, 24, 25, 26 AND gate 27, 28, 29, 30 NOT gate 31 barrel shifter control register

Claims (1)

(57) [Claims] An input data having an effective bit length of 2 ⁿ bits, where n is a natural number, and n + for storing the number of shift bits in synchronization with an external control signal
A 2-bit shift control register; and a bit n of n + 2 outputs of the shift control register
+1 and two output signals of bit n, an externally applied arithmetic and logical shift signal indicating an arithmetic and logical shift,
A shift control circuit that receives the most significant bit of the input data as an input, and outputs an all 0 generation signal, an all 1 generation signal, and a left shift enable signal instructing a left shift of 2 ⁿ bits, and an output n + 2 of the shift control register Lower n of books
The input data based on bit, 2 ⁰ bit, 2 ^bit, ..., and right shifter n stages performing 2 ^n-1 bit right shift, all 0 generation signal is output from the shift control circuit and On the basis of an all 1 generation signal and a left shift enable signal instructing 2 ⁿ bit left shift, all 0 data, all 1 data, or data shifted left 2 ⁿ bits with respect to the output of the n-stage right shifter And a left shifter that outputs the same.