JPH07182140A - Barrel shifter - Google Patents

Abstract

PURPOSE:To perform the shift processing at a high speed by outputting data by the output of a higher order bit of a shift control register, the most significant bit of the input data and an external arithmetic logic shift signal. CONSTITUTION:A shift control circuit 16 contains a shift control register which stores the input data 1 and the shift number 5 synchronously with a shift number write signal 8. Then two pieces of higher order bits are inputted out of six pieces of output of the shift control register together with an external arithmetic shift signal 7 and the input data MSB 6. At the same time, the generation signals of all-0 and all-1 are outputted together with an enable signal 2 which includes a left shift grant signal. Meanwhile the right shifters 11-14 of four stages perform the right shift of bits 1, 2, 4 and 8 of the input data 1 based on lower four bits out of the output of the shift control register. Then a left shifter 15 outputs the data on all-0 or all-1 or the data shifter to the left by 16 bits against the output of the right shifter based on the signal 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for executing a data shift process. More specifically, when a shift process of more than the data word tone is requested for the originally processed data tone, it is detected. The present invention relates to a barrel shifter that performs a shift process at high speed by performing the above process.

[0002]

2. Description of the Related Art In a processor used for signal processing, image processing, etc., a barrel shifter is used to perform digit alignment and bit alignment of data at high speed.

In these conventional barrel shifters, when the effective bit length of data is set to 2 ⁿ , a shift control register for instructing the number of shift bits prepares a bit length of n + 1 bits, and 2 ⁿ -1 bit left shift and 2 ^n. Bit shift right is controlled.

However, in the case of handling floating-point data by a fixed-point arithmetic unit, for example, when data having effective bit lengths of 2 ⁿ are multiplied, data having 2 ⁿ in the exponent part are multiplied. In this case, the exponent part of the multiplication result is the addition of the exponent parts and becomes 2 ^{n + 1} , and the barrel shifter by the shift control register having a bit length of n + 1 bits cannot be suppressed. Normally, in this case, the software determines whether or not the number of shift bits is within the bit length of the shift control register. If the number of shift bits does not fit, the output data is corrected (converted to all 0s and all 1s). Therefore, one extra step is required for the determination, and the execution speed becomes slow.

Therefore, there is a method of processing by hardware in order to speed up the processing. FIG. 3 is a block diagram of a conventional barrel shifter (for example, logic design by LSI P.46-48, author = Satoshi Okugawa, Kyoritsu Publishing Co., Ltd.)
Is shown. In the figure, 1 is input data to be shifted, 11 to 14, 32, and 33 are right 1 bit, 2 bits, and 4 respectively corresponding to each bit of an enable signal 4 described later with respect to the input data 1. bit,
1-bit right shifter, 2-bit right shifter, 4-bit right shifter, 8-bit right shifter, 16-bit right shifter, which performs 8-bit, 16-bit shift, and left 32-bit shift
32-bit left shifter, 5 is an externally applied shift number, 8 is an externally applied shift number write signal, 31
Stores the shift bit number 5 in synchronization with the shift number write signal 8 from the outside, and shifters 11 to 14, 32 and 33
The 6-bit shift control register 4 which outputs the enable signal 4 to 4 has bits 0 to 5 for the 1-bit right shifter 11, the 2-bit right shifter 12, and the 4-bit right shifter 1, respectively.
3, 8-bit right shifter 14, 16-bit right shifter 32,
The enable signal 3 corresponding to the 32-bit left shifter 33 and controlling the shift is the final output data of the 32-bit left shifter.

In the conventional barrel shifter configured as described above, the shift number 5 is the shift number write signal 8 from the outside.
The right shifters 11 to 14 and 32, and the left shifter 33 shift according to the values of bits 0 to 5 of the enable signal 4 stored in the shift control register 31 and output the output data 3.

[0007]

However, in such a conventional barrel shifter, when the effective bit length of data is originally set to 2 ⁿ , the bit length of the shift control register for instructing the number of shift bits is n + 1 bits, and the shifter also has n + 1 bits.
Although it is sufficient to prepare a shifter of stages, an extra shifter is required, the circuit scale becomes large, and the processing speed becomes slower by one shifter.

The present invention solves the above-mentioned conventional problems, and by adding hardware having a relatively small circuit scale, the configuration of the barrel shifter when the effective bit length is 2 ⁿ is 1 It can be composed of n + 1 stages with a reduced number of stages,
The purpose is to perform high-speed shift processing.

[0009]

In order to achieve the above object, a barrel shifter of the present invention synchronizes input data having an effective bit length of 2 ⁿ bits, where n is a natural number, and a shift bit number in synchronization with an external control signal. An n + 2-bit shift control register for storing, two bits n + 1 and n out of the output n + 2 of the shift control register, an arithmetic logic shift signal for instructing arithmetic and logical shift given from the outside, and the input A shift control circuit that receives the most significant bit of data as an input and outputs an all 0 generation signal, an all 1 generation signal, and a left shift enable signal that instructs 2 ^n- bit left shift; and n + 2 outputs of the shift control register. Of which
The input data based on n lower bits, 2 ⁰ bit,
2 ^1- bit, ... 2 ^n- bit right shifter for shifting right, and all 0s output from the shift control circuit
Based on the generated signal, the all 1 generated signal, and the left shift enable signal instructing a 2 ^n- bit left shift, all 0 data, all 1 data, or left 16 bit shift is made to the output of the right shifter of the n stages. And a left shifter that outputs the selected data.

[0010]

According to the present invention, with this configuration, all 0 data is output at the final stage (n + 1 stage) of the shifter by the output of the upper 2 bits of the shift control register, the most significant bit of the input data, and the arithmetic logic shift signal given from the outside. , Or all 1 data, or 16-bit left-shifted data output with respect to the input data, the shift processing equivalent to that of the conventional barrel shifter in FIG. 3 can be performed at high speed.

[0011]

EXAMPLE A barrel shifter according to an example of the present invention,
A description will be given with reference to the drawings.

FIG. 1 is a block diagram of a barrel shifter device according to an embodiment (n = 4) of the present invention. 1 is input data, 2 is an enable signal from a shift control circuit 16 described later, 3 is output data, 5 is the shift number, 6 is the MSB of the input data, 7 is an arithmetic shift signal, 8 is a shift number write signal, and 11 is 1-bit right shifter, 12 is 2-bit right shifter, 13 is 4-bit right shifter, 14 is 8-bit right shifter, and 15 is a 16-bit left shifter having a correction function of output data. The barrel shifter section is composed of 11 to 16. ing. Reference numeral 16 is a shift control circuit described later.

FIG. 2 shows details of the shift control circuit 16. 31 is a barrel shifter control register, 21 is O
R gates, 22, 23, 24, 25 and 26 are AND
Gates 27, 28, 29 and 30 are NOT gates. Bit 5 and bit 4 of the barrel shifter control register 31, the input data MSB6, and the arithmetic shift signal 7 are 21
.. to 30 gate groups, as shown in the figure. Bits 5 to 0 of the barrel shifter control register, the output signal of the OR gate 21 and the output signal of the AND gate 24 are used as the barrel shifter enable signal 2 for the barrel shifter. Connected to the department.

The operation of the barrel shifter device constructed as described above will be described with reference to FIGS. 1 and 2.

First, in the shift control circuit of FIG. 2, the effective bit length of input data is 16 bits. In the barrel shift control register 31, a positive number is set when performing a left shift, and a negative number (two's complement) is set when performing a right shift.

In the barrel shifter control register 31,
When the left shift overflows, that is, when bit 5 is 0 and bit 4 is 1, the output data 0 correction signal is output.

When the right shift overflows, that is, when the bit 5 is 1 and the bit 4 is 0, the MSB of the input data is 0, or the MSB of the input data is 1 and the logical shift is performed (the arithmetic shift signal is 0). Output data is 0
The correction signal is output.

When the right shift overflow occurs and the MSB of the input data is 1 and the arithmetic shift is performed (when the arithmetic shift signal is 1), the output data 1 correction signal is output.

At this time, in the barrel shifter device of FIG. 1, the final stage 16-bit left shifter corrects all bits of the output data to 0 by the output data 0 correction signal, and outputs all the output data by the output data 1 correction signal. Correct the bit to 1.

As described above, in the present invention, the 6-bit shift control register 31 for storing the input data 1 of 16 bits and the shift number 5 in synchronization with the shift number write signal 8 is used.
Of the six outputs of the shift control register 31, two of bit 5 and bit 4, an arithmetic and logic shift signal 7 externally applied to instruct arithmetic and logical shift, and MSB 6 of input data are input. , An all 0 generation signal, an all 1 generation signal, and an enable signal 2 including a left shift enable signal for instructing a 16-bit left shift, and an output 6 of the shift control register 31.
In the shift control circuit 1, the right shifters 11 to 15 of four stages for right shifting the input data 1 by 1 bit, 2 bits, 4 bits and 8 bits based on the lower 4 bits of the book, and the shift control circuit 1
Based on the enable signal 2 including the all 0 generation signal, the all 1 generation signal, and the left shift enable signal for instructing the 16-bit left shift, the all 0 data is output to the output of the right shifter of the four stages. , Or all 1 data,
Alternatively, by providing the left shifter 15 that outputs data shifted by 16 bits to the left, overflow of shift data can be detected, data can be corrected, and high-speed shift processing can be executed.

[0021]

As described above, according to the present invention, shift data overflow can be detected and data can be corrected and shift processing can be executed at high speed without adding large hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of a barrel shifter according to an embodiment of the present invention.

FIG. 2 is a block diagram of the shift control circuit.

FIG. 3 is a block diagram of a conventional barrel shifter device.

[Explanation of symbols]

 1 Input data 2 Enable signal from shift control circuit 3 Output data 5 Shift number 6 Input data MSB 7 Arithmetic shift signal 8 Shift number write signal 11 1 bit right shifter 12 2 bit right shifter 13 4 bit right shifter 14 8 bit right shifter 15 16-bit left shifter 16 shift control circuit 21 OR gate 22, 23, 24, 25, 26 AND gate 27, 28, 29, 30 NOT gate 31 Barrel shifter control register

Claims (1)

[Claims] 1. Input data having an effective bit length of 2 ⁿ bits, where n is a natural number, and n + for storing a shift bit number in synchronization with an external control signal.
A 2-bit shift control register, and bit n of the output n + 2 of the shift control register
Two output signals of +1 and bit n, and an arithmetic logic shift signal for instructing arithmetic and logic shift given from the outside,
A shift control circuit that receives the most significant bit of the input data and outputs an all 0 generation signal, an all 1 generation signal, and a left shift enable signal for instructing a 2 ^n- bit left shift; and an output n + 2 of the shift control register. The lower n in the book
The input data based on bit, 2 ⁰ bit, 2 ^bit, ..., and right shifter n stages performing 2 ^n-1 bit right shift, all 0 generation signal is output from the shift control circuit and Based on the all 1 generation signal and the left shift enable signal for instructing a 2 ^n- bit left shift, all 0 data or all 1 data or left 2 ⁿ bit shifted data with respect to the output of the right shifter of the n stages. Barrel shifter equipped with a left shifter that outputs the.