JPH05282132A - Peak/bottom holding circuit - Google Patents

Abstract

PURPOSE:To shorten a processing time, to reduce soft program development load and to contract a circuit size such as a memory space in an instruction ROM. CONSTITUTION:This peak/bottom holding circuit is provided with a serial data input 11, an exclusive OR 3 for successively comparing bits of outputs from a shift register 8 storing preceding peak/bottom data, a reset-added D type flip flop(FF) 5 holding the data bit of the input 11 when data bits are different and constituted so as to be reset by a start signal 2 indicating the division of data, a selector 7 for selecting the output of the shift register 8 and the serial data input 11 by using the output of the FF 5 as a select signal, an AND 4 for controlling a clock input to the FF 5, and a set-added D type FF 6 to be set up by the start signal 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak / bottom hold circuit, and in particular, it compares the size of a plurality of bits serially transmitted for each frame in bit units and successively updates large data or small data. It relates to a peak / bottom hold circuit.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, a peak / bottom hold circuit of this type converts externally input serial data 14 of an input terminal 1 from serial to parallel (S / P).
A conversion circuit 13, an arithmetic operation circuit (ALU) 18 including a full adder, a register 9 for latching a microcode, and the contents of the microcode, the S
A / P conversion circuit 13 and a programmable logic array (PLA) 10 that generates a control signal for controlling a register 15 that holds data after comparison are configured.

First, in the S / P conversion circuit 13, serial DATA 14 is converted from serial to parallel, then transferred to the ALU 18 via the data bus 16, and then stored in the register 15 up to the previous frame. / By transferring the minimum data to the ALU 11 via the data bus 16, subtracting it from the data transferred from the S / P conversion circuit 13 already stored inside the ALU 18, and caring for the carryout 12 generated as a result, The peak / bottom hold is performed by determining the magnitude and transferring either one of the data as the update data to the register 15.

[0004]

The above-mentioned conventional peak / bottom hold circuit uses a microcode instruction to
Carry out the subtraction function of ALU 18
Since the size is determined by 2, AL from the register group
A total of about 5 machine cycles are required to transfer data to U18 and execute subtraction.
The processing time is more than twice as long as the number of bits of 8), and there is a drawback that the software program development is burdened.

Further, depending on the signal to be processed, there is a drawback that all the processing cannot be executed within the allowable processing time and overflow may occur, and since the microcode increases, the instruction for storing the microcode software is also increased. The drawback is that the ROM memory space also increases, and a new ALU is required to realize this function.
11 and the PLA 10 are disadvantageous in that the circuit scale becomes very large.

It is an object of the present invention to provide a peak / bottom hold circuit which solves the above-mentioned drawbacks and enables necessary processing within an allowable processing time even if the circuit scale is small.

[0007]

The structure of the peak / bottom hold circuit according to the present invention comprises a shift register circuit for storing serially input data, and an output of this shift register and serial data externally input. The exclusive OR circuit that compares bits corresponding to the same rank and the output of the exclusive OR circuit determines the data bit on the external input serial data side when the shift register circuit and the value of the external input serial data are different. When the D-type flip-flop circuit with reset and the circuit for generating the clock input signal and the clock input signal are generated once within one frame of the external input serial data, the clock is held until the data of the next frame is input. A D-type flip-flop circuit with a set for inhibiting generation and the shift register circuit Characterized by comprising a selector for selecting data to be force.

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of this embodiment shown in FIG.

In FIG. 1, in the present embodiment, an external serial data input (hereinafter referred to as DATA) 11 input at clock φ and MSB first, a clock CK for shifting DATA11 at the falling edge, and a start indicating a frame delimiter of DATA11. Operates with signal 2 and DATA 11 and 1
When there is a bit in which the output of DATA 11 and SR 8 do not match with the exclusive OR (EOR) 3 that compares the peak / bottom data up to the frame before with the shift register (SR) 8 that sequentially holds bit by bit , If there is a mismatched bit in the outputs of the D-type flip-flop (RDFF) 5 with reset for holding the bit data on the DATA 11 side and the DATA 11 and SR 8, the clock is input to the RDFF 5 only once with the bit having the higher bit order. ,
In the subsequent bits, a logical product (hereinafter referred to as AND) 4 for inhibiting clock input, a D-type flip-flop circuit with a set (SDFF) 6 set by the start signal 2,
DATA11 when the output of the RDFF5 is "1",
Further, it is configured by including a selector 7 that outputs the output of SR8 when it is "0".

Next, the operation of this embodiment will be described with reference to FIGS.

The data DADA1 is composed of i (i ≧ 1) bits, the SR8 holds the peak data mi one frame before, and the data ni of the new frame ni.
Is input, up to the i−1th bit, ni = mi,
ni−1 = mi−1, and ni−2 at the i−2nd bit
> Mi-2, that is, ni> mi will be described.

When the start signal (START) 2 becomes active, SDFF6 and RDFF5 are set and reset, AND4 is in the clock generation enable state, and the selector 7 is in the state of inputting the output of SR8 to SR8.

Up to the i-2nd bit, DATA1 and SR
Since the bit outputs of 8 are the same and EOR3 is non-astiative, the clock is not input to RDFF5
The output of FF5 holds the reset state "0", and the selector 7 selects the output of SR8 to be input to SR8. Therefore, mi and mi-1 are sequentially held in SR8 at the falling edge of the clock CK. .. At the falling edge of this clock CK,
When the next data bits ni-2 and mi-2 are input to EOR3, ni-2> mi-2 (that is, ni-2 =
1, mi−2 = 0), the output of EOR3 is CK
It becomes "1" only for one cycle, and ni-2 (= 1), which is the bit data of DATA11, is held and output to the RDFF 5 at the rising edge of the clock φ during that period, and the selector 7 makes ni.
-2 is output, and ni-2 is held in SR8 at the next falling edge of CK.

The output of EOR3 is "1" for one CK cycle.
AND4 becomes "1" at the clock φ during that period, but the clock φ falls and AND4 becomes "1" →
When falling to "0", SDFF6 outputs "0" at the falling, therefore AND4 becomes clock generation disable and RDF is activated until the next START2 becomes active.
No clock is input to F5, and even if ni-4 <mi-4, the RDFF 5 remains in the ni-2 (= 1) state held in the i-2th bit as in the i-4th bit. Inputs the data ni on the DATA 11 side to SR8.

As described above, the data bits are sequentially compared and judged, and if there is a different bit, the SR8 is determined by that bit.
Peak hold is performed by switching the input of.

In the case of bottom hold, S of the selector 7
(Select control signal) Input is inverted or J0,
The bottom hold is realized simply by replacing J1 (data-in input) and changing mi to output when ni> mi.

[0017]

As described above, according to the present invention, the serially input data and the stored previous peak / bottom data are serially compared, and the data is selected. The effect of reducing the software program development load, the processing time, the memory space of the microcode instruction ROM, and the circuit size can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a peak / bottom hold circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional peak / bottom hold circuit.

[Explanation of symbols]

 1 serial data input terminal 2 start signal indicating the beginning of frame 3 exclusive OR (EOR) 4 logical product (AND) 7 selector 8 shift register 9, 15 register 10 programmable logic array (PLA) 11 external serial data input 13 serial / Parallel conversion circuit 18 four arithmetic circuits (ALU)

Claims (1)

[Claims] 1. A shift register circuit for storing serially input data, and an exclusive OR circuit for comparing the output of the shift register and serial data input from the outside in correspondence with bits of the same rank, respectively. A D-type flip-flop circuit with reset for holding a data bit on the external input serial data side when the value of the external input serial data differs from that of the shift register circuit by the output of the exclusive OR circuit, and the flip-flop. A circuit for generating a clock input signal of a circuit and a D-type flip-flop with a set that prohibits clock generation until the clock input signal is generated once within one frame of the external input serial data until the data of the next frame is input. And a shift circuit for selecting the data to be input to the shift register circuit. A peak / bottom hold circuit characterized by comprising a rector.