JPH01100637A - System for preventing runaway of digital signal processing lsi - Google Patents

Abstract

PURPOSE:To miniaturize a device by suppressing forced reset pulses outputted at every termination of respective unit processing periods by processing termination signals outputted in every unit processing period in a normal condition and integrating runaway preventing circuits in an LSI. CONSTITUTION:When the processing of input data inputted in one unit processing period is normally terminated, a processing termination flag ZRJP is outputted from an arithmetic processing part 10 and a control circuit 7 to receive this sets a jump flag JP and sends this flag to a runaway preventing circuit 4. Then, when the flag JP arrives, the circuit 4 controls a forced reset pulse RP generated by the termination of the unit processing period by a timing generating circuit and stops sending it. When the processing falls into an infinite loop and goes into a runaway condition while a processing program is executed, an unconditional jump instruction is not sent to the circuit 7, the flag JP is not outputted from the circuit 7 and the forced reset pulse RP generated from the circuit 4 resets a counter 3, a decoder 2 and the circuit 7 without being suppressed by the flag JP.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a runaway prevention method for a digital signal processing LSI that has a built-in processor controlled by a program stored in a ROM and encodes audio or image input signals. The purpose is to provide a runaway prevention method that can be integrated into a digital signal processing LSI without the need to change the configuration. In the digital signal processing LSI, a processing program is sequentially read from the first address of the program ROM every reference clock giving a unit processing period, and processing of input data is repeatedly executed in the unit processing period. An unconditional jump instruction to the first address of the ROM is added to the final step of the processing instruction of the processing program to be processed, and a jump flag is output when this unconditional jump instruction is read. The device is configured to suppress a forced reset pulse for returning the program read address to the start address, which is generated every time the unit processing period ends.

[Industrial application field]

The present invention relates to a runaway prevention method for a digital signal processing LSI that has a built-in processor that is controlled by a program stored in a ROM and that encodes audio or image input signals.

[Conventional technology]

A digital signal processing LSI 100 having a built-in program-controlled processor as shown in FIG. 5 is used for encoding processing of audio signals, image signals, etc., or high efficiency encoding processing such as information compression.

This digital signal processing LSI 100 includes an arithmetic processing section 51
, a control section 52, and an input/output circuit 53 are integrated on a chip with high density together with other necessary circuits, and the arithmetic processing section 51 is an arithmetic logic unit (ALU) 5.
4, accumulator 55, registers 56, 57, RAM
The control section 52 is composed of a program ROM 59, a program counter 60, an instruction decoder 61, and a control circuit 62 that generates various control signals. A processing program for compressing input data such as audio and images, for example, is written in advance.

The control circuit 62 is provided with a mask clock Cm for operating this LSI and a reference clock Cs that provides a repetition period of signal processing.
A processing program written in the program ROM 59 in units of one cycle is read out sequentially from the first address, and the data input via the external bus is processed by this program in the arithmetic processing unit 51, and the processing result is outputted again to the external device as output data. It is configured to output through the bus.

In the above digital signal processing LSI, a processing program written in the program ROM 59 is repeatedly executed on input data whose unit processing period is one cycle given by the reference clock Cs, and the processing results are output one after another. However, during the execution of this process, the address circuit, decoder, or control circuit may become unable to execute the process as programmed due to fluctuations or surges in the LSI's supply voltage, and in the worst case, the process may fail. It may fall into an infinite loop and no output will be made to the outside within the unit processing period, resulting in a so-called runaway state.

In order to prevent such runaway accidents, conventional runaway prevention circuits are provided as shown by reference numeral 63 in FIG. 5, and this conventional runaway prevention circuit 6.

3 is an input/output control signal for data input/output control.
It detects the potential states of "H" and "L" and performs runaway prevention processing suitable for this system. Therefore, it is necessary to redesign this runaway prevention circuit every time the processing program changes. Since the runaway prevention circuit is externally attached to the digital signal processing LSI, it has been difficult to miniaturize the device.

Note that FIG. 5 shows that the reset output of the runaway prevention circuit 63 is sent to the control unit 52 of the digital signal processing LSI 100 via the OR circuit 64 together with the power-on reset signal for forcibly resetting the LSI when the power is turned on.
It is shown as being supplied to.

[Problem that the invention seeks to solve]

As mentioned above, the runaway prevention circuit of the conventional digital signal processing LSI has to be redesigned for each processing program written in the program ROM 59, resulting in extremely poor design efficiency. The runaway prevention circuit is a digital signal processing LSI because there is no
It was not possible to integrate them into a single unit, which was an impediment to system miniaturization.

The present invention provides a runaway prevention method that does not require changing the configuration for each system and can be integrated into a digital signal processing LSI.

[Means for solving problems]

As shown in the principle diagram of FIG. 1, it has a built-in processor controlled by a program stored in program R○M1, and has a reference clock C that provides a unit processing period for signal processing.
In the digital signal processing LS1100, the processing program is sequentially read from the first address of the program ROM every s, and the processing of input data is repeatedly executed in the unit processing period. An unconditional jump instruction to the first address of this ROIvl is added to the final step of , and a jump flag JP is added when this unconditional jump instruction is read.
This jump flag suppresses the forced reset pulse RP generated every time the unit processing period ends to return the program read address to the start address.

[For production]

In the principle diagram shown in FIG. 1, an arithmetic processing unit 10 encodes input data such as audio and images inputted from a human output bus 12 via a human output control circuit 11 using a program decoded from a program ROM 1 by a decoder 2. The data is compressed by digitization, etc., and the processed output is sent from the human output control circuit 11 to the human output bus 12.

The above processing uses one clock period of the reference clock Cs as a unit processing period and processes the input data input during this period, and in the present invention, the processing of the input data input during this unit processing period is completed. Then, the processing end flag ZRJP is configured to be output from the arithmetic processing circuit 10, for example, and this processing end flag resets the program counter 3 via the OR circuit 13.
When the next reference clock is input and data input during this unit processing period is processed, the program is read from the start address of the program ROMI.

The timing circuit 5 of the runaway prevention circuit 4 outputs a forced reset pulse RP when the unit processing period T determined by the reference clock Cs that provides one cycle of signal processing ends, but the control circuit 7 detects the processing end flag ZRJP. If so, a jump flag JP is applied to the suppression circuit 6 of this runaway prevention circuit 4, and suppresses the forced reset pulse RP from this timing circuit.

If the processing of the program falls into an infinite loop during execution and becomes abnormal, the jump flag JP will not be output from the control circuit 7, and the runaway prevention circuit 3 will output a forced reset pulse RP to reset the OR. It is applied to the program counter 3 via the circuit 13, and resets the program counter so that the read address of the program ROMI becomes the first address of this ROM, and at the same time resets the decoder 2 and the control circuit 7 to start the next reference clock. Processing of input data is restarted after waiting for the arrival of Cs.

〔Example〕

Figure 2 shows a digital signal processing L configured by applying the present invention.
This shows one embodiment of SI, and components corresponding to those shown in FIG. 1 are shown with the same reference numerals.
The configuration of the arithmetic processing section 10 is the same as the arithmetic processing section 51 shown in the conventional example shown in FIG. 5, so the same reference numerals as in FIG. A detailed explanation of the explained portions will be omitted.

When the system is powered on, the OR circuit 13 in FIG.
A power-on reset is applied via the OR gate 13' corresponding to , the decoder 2 and the control circuit 7 are reset, and at the same time, the program counter 3 is also reset so that its address output becomes address #0 of ROM 1, and the processing begins. Prepare for the start of. And the reference clock C
When s is given, the LSI 100 uses the mask clock Cm
processing of the input data as described above.

The program counter 3 increments its address by +1 by the +1 circuit 14, reads out the processing program of the program ROMI sequentially from address #0, decodes it with the instruction decoder 2, sends it to the arithmetic processing section 10, and outputs it to the human output control circuit 11. It processes the data read in according to this program, and outputs the processed data to the output bus 12 via the input/output control circuit 11.

When the processing of the input data input in one unit processing period is normally completed, the processing end flag ZRJP is output from the arithmetic processing unit lo, and the control circuit 7 that receives this outputs the jump flag J.
Set P and send this flag to the runaway prevention circuit 4.
When the jump flag JP arrives, the runaway prevention circuit 4 suppresses the forced reset pulse RP generated by the timing generation circuit at the end of the unit processing period, and stops sending it.

If the processing program falls into an infinite loop or goes out of control during execution, the unconditional jump command ZRJ
P is not sent to the control circuit 7, the jump flag JP is not output from this control circuit, and the forced reset pulse RP generated from the timing circuit of the runaway prevention circuit 3 is not inhibited by the jump flag JP and is output from the program counter 3. , to the decoder 2 and the control circuit 7 to reset these circuits.

As a result, the forced reset pulse RP is transmitted from the runaway prevention circuit 4 to the program counter 3 via the OR circuit 13'.
The decoder 2 and control circuit 7 are reset and kept in a standby state until restarted by the next arriving reference pulse.

FIG. 3 shows an embodiment of the runaway prevention circuit 3, which is composed of a shift register 31, a latch circuit 32, AND circuits 33, 34, 35, and inverters 36, 37.

FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. 3, and the reference clock Cs shown in FIG. The frequency-divided clock Cd is a clock signal with a frequency much higher than the frequency of the reference clock Cs obtained by dividing the mask clock Cm for operating the digital signal processing LSI, for example, the frequency of the reference clock Cs. When the frequency of the divided clock Cd is 8 kHz, the frequency of the divided clock Cd is 2 MH2.

The shift register 31 shifts the reference clock Cs by the frequency-divided clock Cd as shown in FIG. 4(b).

The divided clock C as shown in (C) and (d), respectively.
It outputs three shift outputs Qa, Qb, and Qc delayed by a pulse width t corresponding to one clock of d.

The Qa output of the shift register 31 is inputted to one input terminal of the AND circuit 33 via the inverter 36.
Similarly, the Qb ratio output of the shift register is input to the other input terminal. Further, the Qb output of the shift register is inputted to one input terminal of the AND circuit 34 via the impark 37, and the shift output Qc is inputted to the other input terminal.

Therefore, from each output terminal of the AND circuits 33 and 34,
As shown in FIGS. 4(e) and 4(f), the pulses PI and P2, which are given a phase difference of pulse width t corresponding to one clock of the divided clock Cd obtained by dividing the master clock, are applied to the reference clock Cs. It is output every cycle.

If there is no abnormality in the signal processing operation of the digital signal processing LSI, the jump flag JP shown in FIG. from circuit 7.

The latch circuit 32 is set as shown in the figure (f) by receiving this jump flag JP.
It is reset by receiving the pulse P2 from the AND circuit 34 shown in FIG. 3 at the reset input terminal R, and outputs the suppression signal MS shown in FIG.

Therefore, during normal operation, the pulse P1 applied from the AND circuit 33 to one input terminal of the AND circuit 35 is suppressed by the suppression signal MS, and no cent pulse is sent out from the AND circuit 35.

On the other hand, in the case of a runaway state, the latch circuit 32 is not given the jump flag JP shown by the dotted line in FIG.
S is not generated, and the pulse P1 outputted by the AND circuit 33 is outputted as a reset pulse R as shown in FIG. 4(i) without being suppressed by the suppression signal MS.

This reset pulse R resets the program counter 3 in FIG. 2, and also resets the decoder 2 and control circuit 7 to their initial states, automatically escaping from a runaway state such as an infinite loop. can do.

〔Effect of the invention〕

In the present invention, the forced reset pulse that is output at each end of each unit processing period is suppressed by the processing end signal that is output at each unit processing period under normal conditions, so that runaway program processing can occur. There is no longer a need to detect this using a human output control signal from the input/output circuit, and there is no need to design a runaway prevention circuit for each processing program, so the runaway prevention circuit can be integrated into the LSI in advance. , this makes it possible to achieve the special effect of being able to downsize the system.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a diagram showing an embodiment of a runaway prevention circuit, and Fig. 4 is a diagram showing the operation of this runaway prevention circuit. A time chart for explanation, FIG. 5 is a diagram showing a conventional example. ■ is a program ROM, 2 is a decoder, 3 is a program counter, 4 is a runaway prevention circuit, 5 is a suppression circuit, 6 is a timing circuit, 7 is a control circuit, Cs is a reference clock, ZR
JP is an unconditional jump command to the first address of ROMI, J
P is a jump flag, and RP is a forced reset pulse. Patent applicant Fujitsu Limited

Claims (1)

[Claims] It has a built-in processor that is controlled by the program stored in the program ROM, and the signal processing unit processing period (
In the digital signal processing LSI (100), the processing program is sequentially read out from the first address of the program ROM every time the reference clock (Cs) gives the reference clock T), and the processing of input data is repeatedly executed in the unit processing period. An unconditional jump instruction to the first address of this ROM is added to the final step of the processing instruction of the processing program written in the program ROM, and when this unconditional jump instruction is read, a jump flag (J
P), and the jump flag suppresses a forced reset pulse generated every time the unit processing period ends to return the program read address to the start address. A runaway prevention method for digital signal processing LSI.