JPH064171A - Method and circuit for generating timing signal - Google Patents

Abstract

PURPOSE:To provide a timing signal generation circuit capable of generating two kinds of timing signals used in the same control with a small scale circuit. CONSTITUTION:A fundamental timing signal generating part 11 is a pulse generation circuit, and outputs a start pulse 12. A signal generation control part 13 is equipped with a shift register 41, and outputs a start-up signal 14 in which time adjustment is applied to the start pulse 12. A synchronizing signal generating part 15 is equipped with a flip-flop 42, and a strobe signal generating part 16 is equipped with a shift register 43. A strobe signal generating part 16 receives the start-up signal 14, and outputs a strobe signal STB, and performs the self-feedback of the final output, and generates the strobe signal repeatedly until the next start pulse 12 is outputted. The synchronizing signal generating part 15 outputs a reset signal 17 from the input of the start-up signal 14, i.e., an in-period synchronizing signal FSYN until the output of the shift register 43 is inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing signal generating method and a timing signal generating circuit for generating two kinds of timing signals used for the same control and having different characteristics.

[0002]

2. Description of the Related Art For example, in a synchronous control circuit in an interface between devices or between cards or an image control circuit in an image processing device for a television image, a synchronous signal (synchronous control circuit) and a vertical synchronous signal (image The so-called control circuit) (first pulse signal) and the so-called strobe signal (synchronization control circuit) or horizontal synchronization signal (image control circuit) (second pulse signal) have different characteristics. Two types of timing signals are used.

Since these two kinds of timing signals having different characteristics are used for the same control, they are generated based on one basic timing signal. However, in the past, from the viewpoint of facilitating design and maintenance, the basic signal is basically used. Specifically, the method is as shown in FIG.

That is, in FIG. 7, A is a functional block that generates a basic timing signal and controls the whole.
B is a functional block that generates a first pulse signal, C is a functional block that generates a second pulse signal, and D is a functional block for ensuring the reliability of the operation of the circuit. , C, and D are provided in parallel, and B, C, and D independently receive an operation mode instruction (control) from A, perform a predetermined operation, and give the operation status (status) to A.

In this way, it is possible to design in each functional block unit and to adopt a method of combining them, so that the design becomes easy and the maintenance becomes easy.

However, in the system shown in FIG. 7, since circuits that perform similar operations in B, C and D are duplicated and exist, the circuit scale tends to increase, and each line of control and status has each functional block. Since it is required for each, the number of parts increases and it is difficult to miniaturize the circuit. So, in actual use,
The system shown in FIG. 8 in which the basic configuration of FIG. 7 is modified is adopted. In the following, the first pulse signal will be referred to as a synchronization signal,
The second pulse signal will be described as a strobe signal.

That is, in FIG. 8, B and C receive an operation mode instruction (control) from A and generate a synchronization signal (FSYN) and a strobe signal (STB), respectively.
D does not notify the operation status (status) to A, and D exchanges control and status with A and monitors the operation of B and C,
The circuit and the control are simplified. A concrete circuit configuration of the system shown in FIG. 8 is as shown in FIG.

In FIG. 9, the timing signal generating circuit includes a basic timing signal generating section 91 and a synchronizing signal generating section 93 connected in parallel to the basic timing signal generating section 91 via a data bus 92.
The strobe signal generation unit 94 and the timing signal generation monitoring unit 95 are included. The basic timing signal generation unit 91 is mainly composed of a counter circuit, while the synchronization signal generation unit 93, the strobe signal generation unit 94 and the timing signal generation monitoring unit 95 are mainly the decoder and the comparator, respectively. Is composed of.

In short, the synchronizing signal generating section 93, the strobe signal generating section 94, and the timing signal generating and monitoring section 95 take in the same count value that the basic timing signal generating section 91 sends to the data bus 92, and decode it. In response to the instruction (control) of the operation mode, the synchronizing signal (FSYN) 96, the strobe signal (STB) 97, and the status 98 are output during the period in which the fetched count value matches the set value.

[0010]

The above-mentioned conventional timing signal generation method has an advantage that circuit design is easy, but has the following problems. First, the basic timing signal generator needs to be configured as a dedicated circuit, is difficult to share, and the synchronization signal generator and strobe signal generator have the same configuration, but they are independent dedicated circuits.
It is difficult to reduce the size of the timing signal generation circuit because the third circuit for monitoring them is necessary.

In the same device, a plurality of sets each including the first pulse signal and the second pulse signal may be used, but in the above-described conventional timing signal generation system, one circuit is used. It is difficult to generate such multiple sets of timing signals. Therefore, conventionally, it is necessary to use a plurality of timing signal generation circuits having different contents, but since the circuit scale of one circuit is large, the number of circuits that can be mounted on one card is small, and improvement is desired. For example, a standard double euro size card can mount 60 ICs, but the conventional timing signal generation circuit is composed of about 15 ICs, so only four kinds of timing signal generation circuits should be mounted. You cannot do it.

Further, since the synchronizing signal generating section, the strobe signal generating section and the like perform different operations under the same control of the basic timing signal generating section, the data bus method is adopted for simplification of the circuit. When the generator is set to a different card, a certain number of pins (8, 16, 32, etc.) of the I / O connector of the card are monopolized by the data bus and limit I / O of other signals. . In other words, the flexibility of card layout design is narrowed.

It is an object of the present invention to provide a timing signal generating method and a timing signal generating circuit which can miniaturize the circuit and increase the degree of freedom in the layout design of the card.

[0014]

To achieve the above object, a timing signal generating method and a timing signal generating circuit according to the present invention have the following configurations. That is, the timing signal generating method according to the first aspect of the present invention includes: a circuit for outputting an operation start instruction (pulse signal); and a circuit for outputting an operation start instruction (pulse signal) time-adjusted in response to the operation start instruction. A circuit c for outputting a first pulse signal having a pulse width of a predetermined time from an operation start instruction; a circuit d for repeatedly outputting a second pulse signal of a predetermined width in response to an operation start instruction; And circuit C, circuit B, any one circuit of circuit C and circuit D, and the other circuit of circuit C or circuit D are arranged in this order; A → Circuit B → One of circuit C and circuit D → One of the other circuit of circuit C and circuit D is transmitted from the previous stage to the subsequent stage in order; The operating condition is transmitted from the latter stage to the previous stage in order Is characterized by the following.

The timing signal generating method according to the second aspect of the present invention includes a circuit (i) for outputting an operation start instruction (pulse signal); one or two operation start instructions (pulse signal) which are time-adjusted in response to the operation start instruction. ) Outputting a circuit b; a circuit c outputting a first pulse signal having a pulse width of a predetermined time from an operation start instruction; and a second pulse signal having a predetermined width repeated in response to an operation start instruction The circuit B for outputting is provided, and the circuit B and the circuit B are arranged in series; the circuit C and the circuit D are arranged in parallel to the circuit B; It defines a predetermined time from the instruction;

In the timing signal generating method of the third invention, the first pulse signal and the second pulse signal having a predetermined width are generated based on the basic timing signal, and the duration of the first pulse signal is set to the second pulse signal. Is defined according to the timing of occurrence of.

The timing signal generating circuit of the fourth invention is 1
A circuit for outputting one basic timing signal (pulse signal); a circuit for outputting a first pulse signal having a pulse width between the input of the basic timing signal and the input of a reset signal; and a circuit for receiving the basic timing signal And a circuit for repeatedly generating the second pulse signal having a predetermined width and outputting the reset signal.

The timing signal generating circuit of the fifth invention is 1
A circuit for outputting one basic timing signal (pulse signal); a circuit for receiving one starting signal or two starting signals having a time difference in response to the basic timing signal; the one starting signal or the two starting signals A circuit for outputting a first pulse signal having a pulse width from the input of the one start signal to the input of the reset signal;
A circuit that receives the one activation signal or the other activation signal of the two activation signals and repeatedly generates a second pulse signal having a predetermined width, and outputs the reset signal. It is a thing.

The timing signal generating circuit of the sixth invention is n
A circuit for outputting (n ≧ 2) basic timing signals;
N circuits that output two types of timing signals (first pulse signal and second pulse signal) based on one of the n basic timing signals; and, each of the n circuits includes A circuit for outputting a first pulse signal having a pulse width between the input of the corresponding basic timing signal and the input of the reset signal; and repeatedly generating a second pulse signal of a predetermined width in response to the basic timing signal. And a circuit that outputs the reset signal.

The timing signal generating circuit of the seventh invention is n
A circuit for outputting (n ≧ 2) basic timing signals;
A circuit for receiving the n basic timing signals and outputting n startup signals or each of the n basic timing signals in the form of two startup signals having a time difference;
N circuits that output two kinds of timing signals (first pulse signal and second pulse signal) based on one start signal of the n start signals or two start signals having the time difference. Each of the n circuits has a first pulse signal having a pulse width from a start signal input to a reset signal input of one corresponding start signal or two start signals having a time difference. A circuit that outputs the reset signal while repeatedly generating a second pulse signal having a predetermined width in response to the other activation signal of the one activation signal or the two activation signals having a time difference. It is characterized by including.

[0021]

Next, the operation of the timing signal generating method and the timing signal generating circuit of the present invention configured as described above will be described. In the present invention, each circuit element is basically arranged in series (first invention to fifth invention), an operation start instruction and time adjustment thereof (first invention, second invention), that is, basic timing. A signal or a start signal (third invention to seventh invention) formed from this basic timing signal are both generated as pulse signals, and at least a circuit for outputting a first pulse signal and a circuit for outputting a second pulse signal. And work together. Specifically, the duration of the first pulse signal is defined by the generation timing of the second pulse signal (second invention to seventh invention).

Therefore, the decoder need only be provided in the circuit for generating the basic timing and need not be provided in the other element circuits, and the circuit for generating the first pulse signal and the circuit for generating the second pulse signal cooperate with each other. Since it does not require a special circuit for controlling all of them, the circuit scale is greatly reduced. Since the circuit that generates the basic timing only needs to generate the basic timing, it can be shared with other external circuits or can be substituted by the processor, and the circuit can be downsized also from this point.

Further, since the connection between each element circuit is made by a few control signal lines, the number of pins of the I / O connector of the card that can be used for other signals is significantly increased.
Therefore, even when each element circuit is mounted on a different card, the degree of freedom in the layout design of the card can be increased.

Furthermore, without increasing the circuit scale,
It is possible to easily generate a plurality of types of timing signals (sixth invention and seventh invention).

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of a timing signal generating method according to an embodiment of the present invention. The timing signal generation system of the present invention is basically E, F, G, H as shown in FIG.
4 functional blocks are arranged in series, and E → F → G → H
And the operation mode instruction (control) are transmitted, and H → G → F → E
Is a method of transmitting the operation status (status), that is, a method of operating each functional block in cooperation.

The four functional blocks E, F, G and H are
It is as follows. That is, since the functional block E exchanges control and status with only F, it suffices if it mainly generates a basic timing signal. Therefore, the basic timing signal does not need to have a count value as in the conventional case, but a pulse signal. The overall function is substantially smaller than that of the conventional example A.

The functional block F is mainly intended to control the generation timing of the timing signal generated by G and H in the subsequent stage. Further, G and H are functional blocks that generate a first pulse signal on one side and functional blocks that generate a second pulse signal on the other side. It is adapted to form a predetermined timing signal.

According to the first embodiment, since the respective functional blocks operate in cooperation with each other, the functional block D which is conventionally required.
A considerable thing becomes unnecessary, and it suffices to provide only one functional block E with the circuit that performs the same operation as that of each functional block in the past regarding the transfer of control and status, further reducing the control line and the status line, It is possible to significantly reduce the circuit scale.

Also in this system, G and H can be operated independently as in the conventional B and C, and F is instructed only when the conditions for G and H are instructed. It is also possible for G and H receiving the instruction to ignore the instruction until the processing conditions are satisfied.

By the way, in the system shown in FIG. 1, F, G,
H is an operation mode instruction (control) from the functional block in the previous stage
In response to this, processing is started, and after that processing is ended, instructions (controls) are issued to the functional blocks in the subsequent stage. This is disadvantageous in terms of processing time, but is based on the purpose of reducing the circuit scale. In other words, when a processing start instruction is issued to a subsequent functional block before the processing of its own is started when a processing start instruction is received from a previous functional block, each functional block operates a circuit that performs the same operation. Since it has, it becomes difficult to reduce the circuit scale.

Therefore, as shown in FIG. 2, let us consider a method in which F issues a processing start instruction to G and H in parallel. In FIG. 2, the status from F to E, the status from G and H to F, and the status from G to H are omitted to simplify the control and the circuit. G is FS
YN (synchronous signal) is generated, and H generates STB (strobe signal). In FIG. 2, F performs either an operation for issuing a separate instruction to G and H or an instruction for the same content, but in the case of issuing the same instruction for FIG. 3 and FIG. The configuration is shown.

In FIG. 3, the basic timing signal generator 11 includes, for example, a counter circuit and its output (count value).
And a decoder for receiving the count value, and gives a start pulse 12 obtained by decoding the count value instead of the count value to the signal generation control unit 13 as an instruction (control) to start the processing. That is, in the present invention, the decoder (B, C, and D), which has been conventionally provided, is provided in E (basic timing signal generation section 11) corresponding to A, so that B, C, and D are constituent elements. The G (synchronous signal generating section), H (strobe signal generating section), and F (signal generation control section) corresponding to the above can be significantly downsized.

The basic timing signal generator 11 is
Since it only needs to have a function of generating a start pulse, it can be shared with another circuit having a pulse generation function, and further, a circuit can be realized by an oscillator, a processor, or the like.

The signal generation controller 13 controls the start pulse 1
The activation signal 14 is generated immediately after receiving 2 or after a predetermined time. This is output in parallel to the synchronization signal generator 15 and the strobe signal generator 16. When the activation signal 14 has the same content, the synchronization signal generation section 15 and the strobe signal generation section 16 are connected to the activation signal line in a potato-like manner. In this case, since the start signal 12 itself can be used as the start signal 14,
The signal generation controller 13 can be dispensed with in applications where the output timing of the activation signal 14 is not manipulated.

The synchronization signal generator 15 and the strobe signal generator 16 receive the activation signal 14 in parallel and receive the synchronization signal (FS
YN) and strobe signal (STB) are output, but the synchronization signal generator 15 outputs the synchronization signal (FSYN) until the reset signal 17 is input from the strobe signal generator 16. That is, the two work together. Since the strobe signal is a pulse signal having a predetermined width that is repeatedly generated, this cooperative operation is unidirectional.

FIG. 4 shows a specific example of the configuration of the signal generation control unit 13, the synchronization signal generation unit 15, and the strobe signal generation unit 16. That is, the signal generation controller 13 is mainly composed of the shift register 41, the synchronization signal generator 15 is mainly composed of the flip-flop 42, and the strobe signal generator 16 is mainly composed of the shift register 43.

In FIG. 4, in the signal generation control section 13,
The shift register 41 is initialized by a clear signal CLR from the outside of the figure, but the start pulse 12 from the basic timing signal generator 11 input to the terminal IN is taken in by the clock signal CLK from the outside of the figure and shifted, It is sequentially outputted from the eight output terminals (Q _a ~Q _H) (Fig. 5
(A) to (d)). The above operation is performed every time the start pulse 12 is input. In the illustrated example, the first Q _A output is used as a clear signal and the last Q _H output is used as a start signal in the subsequent stages, but since the pulse width of each output is the same as the pulse width of the start pulse 12, By changing the pulse width of the pulse 12, the pulse width of the output (starting signal) of the signal generation controller 13 can be easily changed.

In the strobe signal generator 16, the shift register 43 is initialized by either the clear signal CLR from outside the drawing or the Q _A output of the shift register 41 (FIG. 5 (E)), but first, the terminal Shift register 4 input to IN
The Q _H output of 1 is taken in by the clock signal CLK (Fig. 5 (f)), shifted, and output from eight output terminals (Q _A ~
Q _H ) are sequentially output. Then, its own Q _H output is given to the terminal IN (FIG. 5 (h) (f)), and the Q _A output of the shift register 41 or the clear signal CLR from outside the figure is given.
The above operation is repeated until is input.

As a result, the strobe signal generator 16
In the illustrated example, the head Q _A output of the shift register 43 is the strobe signal (STB), but this strobe signal is repeatedly generated from the Q _A output to the Q _H output as one cycle (FIG. 5 (g)). (H) (N)). The generation period of the strobe signal can be easily changed depending on which output terminal receives the feedback signal to the terminal IN. In the illustrated example, seven types of selections can be made. If the shift registers are cascaded in multiple stages, the selection range can be expanded.

Further, in the synchronizing signal generator 15, the flip-flop 42 is initialized at the same timing as the shift register 43 and sets the inverted output (bar of Q) to "1" level. The start signal 14 which is the Q _H output of the shift register 41 is taken into the terminal J by CLK, and the inverted output (Q bar) is set to the “0” level,
The Q _H output (reset signal 17) of the shift register 43 is taken into the terminal K and the inverted output (Q bar) is set to the “1” level.

As a result, in the synchronizing signal generator 15,
The synchronizing signal (FSYN) which is at the "0" level is output within the period from the input of the activation signal 14 to the input of the reset signal 17 (FIG. 5 (i)). That is, one sync signal (FSYN) is generated each time the start signal 14 is input, and thus each time the start pulse 12 is output, and its duration is the cycle of the strobe signal (STB) in the illustrated example. (Fig. 5 (ri) (nu)).

Next, according to the timing signal generating system of the present invention, the configuration shown in FIG. 6 is also possible. That is, the basic timing signal generator 61 outputs n start pulses in parallel, and the signal generation controller 62 outputs start signals corresponding to each start pulse, that is, n start signals in parallel.
Then, a synchronization signal generator 63 and a strobe signal generator 64 are provided for each of the n start signals, and n kinds of timing signals [(FSYN ₁ , STB ₁ ), (FSYN ₂ , STB ₂ ), ...
…, (FSYN _n , STB _n )] can be created.

According to this, for example, in the above-mentioned table of the euro size, a circuit capable of generating about 25 kinds of timing signals can be mounted, and two kinds of timing signals (FSYN, STB) can be provided without increasing the circuit scale. It has been shown that a circuit for generating a plurality of

[0044]

As described above, according to the timing signal generating method and the timing signal generating circuit of the present invention,
Basically, each circuit element is arranged in series (first invention-
(Fifth invention), an instruction to start the operation and a time adjustment thereof (first invention, second invention), that is, a basic timing signal or a start signal formed from this basic timing signal (third invention to seventh invention) Are both generated as pulse signals, and at least the circuit for outputting the first pulse signal and the circuit for outputting the second pulse signal operate in cooperation with each other. Specifically, since the duration of the first pulse is defined by the timing of generation of the second pulse (second invention to seventh invention), the decoder may be in a circuit that generates basic timing and other It is not necessary to have it in the element circuit, and the circuit for generating the first pulse signal and the circuit for generating the second pulse signal operate in cooperation with each other, and a special circuit for supervising these circuits is not required. Is greatly reduced. Since the circuit that generates the basic timing only needs to generate the basic timing, it can be shared with other external circuits or can be substituted by the processor, and the circuit can be downsized also from this point. In addition, since the connection between each element circuit is made by a few control signal lines, the I
The number of pins of the / O connector that can be used for other signals is significantly increased. Therefore, even when each element circuit is mounted on a different card, the degree of freedom in the layout design of the card can be increased. Further, the configuration as in the sixth invention or the seventh invention has an effect that it is possible to easily generate a plurality of types of timing signals without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a structural conceptual diagram of a timing signal generating method according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a configuration of a timing signal generating method according to a second embodiment of the present invention.

FIG. 3 is a configuration block diagram of a timing signal generation circuit according to a third embodiment of the present invention.

FIG. 4 is a configuration block diagram of a timing signal generation circuit according to a fourth embodiment of the present invention.

FIG. 5 is a time chart explaining the operation of the circuit according to the fourth embodiment of the present invention.

FIG. 6 is a configuration block diagram of a timing signal generation circuit according to a fifth embodiment of the present invention.

FIG. 7 is a conceptual diagram showing the configuration of a conventional timing signal generating method.

FIG. 8 is a conceptual diagram of a configuration of a conventional timing signal generation method.

FIG. 9 is a configuration block diagram of a conventional timing signal generation circuit.

[Explanation of symbols]

 11 basic timing signal generator 13 signal generation controller 15 sync signal generator 16 strobe signal generator E, F, G, H functional block

Claims (7)

[Claims] 1. A circuit for outputting an operation start instruction (pulse signal); a circuit for outputting a time-adjusted operation start instruction (pulse signal) in response to an operation start instruction; and an operation start instruction A circuit c for outputting a first pulse signal having a pulse width of a predetermined time of; a circuit d for repeatedly outputting a second pulse signal of a predetermined width in response to an instruction to start operation; The circuit B, the circuit C and the circuit D, and the circuit C and the circuit D are arranged in this order; And one of the circuit D and the circuit C and the other circuit of the circuit D and the other circuit are transmitted in order from the preceding stage to the subsequent stage; The operation condition is transmitted in order from the latter stage to the preceding stage; Signal generation method. 2. A circuit for outputting an operation start instruction (pulse signal);
A circuit b for outputting one or two operation start instructions (pulse signals); a circuit c for outputting a first pulse signal having a pulse width of a predetermined time from the operation start instructions; and an operation start instruction And a circuit b for repeatedly outputting a second pulse signal having a predetermined width, and circuit b and circuit b are arranged in series; circuit c and circuit d are arranged in parallel with circuit b; A predetermined time from the instruction to start the operation is defined by a cooperative operation with the circuit D; 3. A first pulse signal and a second pulse signal having a predetermined width are generated based on the basic timing signal, and the duration of the first pulse signal is defined by the generation timing of the second pulse signal. A timing signal generating method characterized by the above. 4. A circuit for outputting one basic timing signal (pulse signal); a circuit for outputting a first pulse signal having a pulse width between the input of the basic timing signal and the input of a reset signal; A circuit which receives the basic timing signal and repeatedly generates a second pulse signal having a predetermined width and outputs the reset signal;
A timing signal generating circuit comprising: 5. A circuit that outputs one basic timing signal (pulse signal); a circuit that outputs one start signal or two start signals having a time difference in response to the basic timing signal; and one start signal Or a circuit that outputs a first pulse signal having a pulse width between the input of one of the two start signals and the input of a reset signal; and the other of the one start signal or the two start signals. And a circuit for repeatedly generating a second pulse signal having a predetermined width and outputting the reset signal, the timing signal generating circuit. 6. A circuit for outputting n (n ≧ 2) basic timing signals; two types of timing signals (first pulse signal and second pulse) based on one of the n basic timing signals. And n circuits for outputting a first pulse signal having a pulse width between the input of the corresponding basic timing signal and the input of the reset signal, respectively. A circuit for receiving the basic timing signal and repeatedly generating a second pulse signal having a predetermined width and outputting the reset signal. 7. A circuit for outputting n (n ≧ 2) basic timing signals; receiving n basic timing signals, each of the n start signals or the n basic timing signals having a time difference. A circuit for outputting in the form of two start signals; two kinds of timing signals (first pulse signal and second pulse signal based on one start signal of the n start signals or two start signals having the time difference); Pulsed signals), and n circuits each of which outputs a start signal from one start signal corresponding to one start signal or two start signals having a time difference. A circuit for outputting a first pulse signal having a pulse width of up to 1; a second pulse having a predetermined width upon receipt of the other activation signal of the one activation signal or two activation signals having a time difference A circuit for repeatedly generating a signal and outputting the reset signal, and a timing signal generating circuit.