JPH0322614A - Multiplexer - Google Patents

Abstract

PURPOSE:To relieve the load of a dynamic bus input by separating a circuit receiving a dynamic input from a circuit receiving a static input. CONSTITUTION:Three inverters 9 controlled respectively by decode signals A, B, C, AND gates 6, 7 receiving a clock K, an OR gate 8 receiving the decode signals A, B, C, an inverter 10, a latch circuit 3 comprising 2 inverters, and an inverter 4 are provided in the multiplexer. Then a data DO transferred to a dynamic bus 1 is fetched in the latch circuit 3 via a clocked inverter 2. Static input data D1, D2, D3 are selected at the clock inverter 9 by using control signals A, B, C. Thus, the input latch using only 2 systems is obtained by the separation of the static and dynamic buses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexer, and particularly to a multiplexer that has a large number of inputs and receives input from a dynamic bus. [Prior Art] Conventionally, as shown in FIG. 2, this type of multiplexer inputs data DI, D2, and D3 from static output lines 102, 103, and 104 even when inputting a signal DO from a dynamic bus 101. In this case, a common output line 105 is also provided.

The output of the gate 206, which is composed of four AND gates each receiving a clock (K) input and decode signal A, B, C, and D inputs, is output from the inverters 106, 107, 108,
109 and these inverters 10B, 1.07,
Data DO, Di, D2, and D3 are input to 108 and 109, respectively.

From the output line 105, two stages of inverters 202 and 203 are connected.
is output as output 0 via .

The structure of this circuit was simple and required only a small number of elements to form a semiconductor integrated circuit, making it highly efficient. However, the common output line 105 is provided with a capacitor 100 having a capacitance value CO corresponding to the sum of many output capacitance values. This becomes a factor that increases the output delay when the clocked inverters l06, 107, 108, and 109 forming the multiplexer become active. In particular, the input from the dynamic bus 101 is input to the gate 206, which is an AND gate that controls the clocked inverter 106, with no setup time.
The following results in a particularly large output delay. As shown in FIG. 3, this timing chart shows that, with respect to the clock (K) signal, the input from the dynamic bus 101 can be sent by a delay time d0, and the input from the static human power 201 can be sent by a delay time d. This appears as an output O, where time d0 is greater than time d.

[Problem to be solved by the invention]

Since the conventional multiplexer described above is used without distinguishing between the type of input, ie, static or dynamic, the value of the output capacitance 100 added to the multiplexer becomes large, and the output delay occurs especially for the input from the dynamic bus 101. It has the disadvantage of increasing the SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplexer which solves the above-mentioned drawbacks and prevents the delay time from becoming large with respect to inputs from a dynamic bus.

[Means to solve the problem]

According to the structure of the present invention, in a multiplexer which receives dynamic inputs from a dynamic bus and static inputs and shares a common output line, a circuit into which the dynamic inputs are input is provided so as to reduce the addition of the dynamic inputs. , is characterized in that it is separated from the circuit into which the static input is input.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing a multiplexer according to an embodiment of the present invention. In FIG. 1, the multiplexer of this embodiment includes three inverters 9 each controlled by decode signals A, B, and C.
, an AND gate 6 and 7 to which clock K is input, an OR gate 8 to which decode signals A, B, and C are input, an inverter 10, and a latch circuit 3 consisting of two inverters.
and an inverter 4. Inverter 2
Data DO is input to the inverter 9, and data DI, D2, and D3 are input to each of the three inverters 9. AND
The decode signal D is input to the gate 6, and the output of the OR gate is input to the AND gate 7. Data DO transferred to the dynamic bus 1 is taken into the latch circuit 3 via the clocked inverter 2. If the bus 1 to which the data DO is transferred is considered as a negative logic, if an inverter is attached, the output O becomes a positive logic. A signal controlling clocked inverter 2 is generated by gate 6. This gate 6 is a logic gate that receives as input a decode signal D of an instruction taken in from the bus 1 and a clock K. On the other hand, the static input data DI, D2, D3 are inputted by the clock inverter 9 to the respective control signals A, B. Selected by C. These consist of decoded signals A, B, and C for instructions that take in static signals. These three selection signals A,
It is assumed that only one of B and C is selected.
Finally, the clocked inverter 10 enters the latch circuit 3. Gate 8, which is a three-way OR gate, is the [OR] of input signals A, B, and C, and creates a logic for controlling clocked inverter 10 via gate 7. Due to the above separation of static and dynamic, there are only two input latches. Regarding the capacitance, the capacitance value CI of the output line of the inverter 2 shown in FIG.
The capacitance value of the output line of the inverter IO is 02, and the capacitance value of the input line of the inverter IO is C3, but generally C1+02<01+03.
becomes. This is equivalent to Co(
CO:=C1+03).

By separating the dynamic bus input and dynamic bus input, the load on the dynamic bus input can be reduced, and a multiplexer with a latch circuit with less delay can be provided.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing a multiplexer according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a conventional multiplexer,
Figure 3 is a waveform diagram showing the timing operation of the circuit in Figure 2.
It is. 101,1...Dynamic bus, 9,2,1
0,106,107,108,109...Clocked inverter, 3...Latch circuit, 4,2
02,203...Inverter, 6,7,8,2
06...Gate, 102, 103, 104...
...Static input line, 105...i...Output line, 201...Static input.

Claims (1)

[Claims] In a multiplexer that receives dynamic inputs and static inputs from a dynamic bus and shares a common output line, a circuit that receives the dynamic inputs is configured to reduce the load on the dynamic inputs.
A multiplexer characterized in that the static input is separated from a circuit into which it is input.