JPH02222215A - Output buffer for lsi - Google Patents

Abstract

PURPOSE:To avoid the collision of data on a bus when the output of an LSI is connected to the bus by providing a differentiation circuit using a delay circuit and an AND circuit on an input terminal. CONSTITUTION:A delay circuit 11 retarding an input signal from an input terminal 1 and an AND circuit 12 receiving a signal from the delay circuit 11 and the input terminal 1 are provided. That is, a differentiation circuit is constituted of the delay circuit 11 and the AND circuit 12 and a signal having a narrow width of '1' is outputted at an LSI output terminal 9. When LSI output terminals 91-93 are connected by the bus 10, the output from the LSI output terminals 91-93 is short-circuited on the bus 10 due to difference from the delay time in the LSI inside and no large current flows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI, and particularly to a three-state output buffer used for bus connection between LSI outputs.

[Conventional technology]

Conventionally, this type of output buffer has a circuit as shown in FIG. 2. Next, we will explain about FIG. 2. In FIG.
The output of the OR circuit 5 becomes @0', and the output of the NAND circuit 4 becomes @0'.
The output of is 11'. Therefore, the P-channel transistor 7 and the N-channel transistor 8 are in an OFF state, and the LSI output terminal 9 is in an open state.

On the other hand, when %071 is input to output control terminal 2, N
An inverted signal of the signal input from the input terminal 1 is output to the output of the AND circuit 4 and the output of the NOR circuit 5. 3
is a NOT circuit. The same signal is input to P-channel transistor 7 and N-channel transistor 8, and transistors 7.8 can be viewed as a NOT circuit. Therefore, when ``0'' is input to the output control terminal 2, L
The signal at the input terminal 1 is output as is to the SI output terminal 9.

[Problem to be solved by the invention]

As shown in Fig. 3, the above-mentioned conventional sofa has a LS
When connecting I output terminals 9□ to 93 with 0 on the bus,
The output control signal is controlled so that the output terminals 91 to 9° of the LSI do not become output states at the same time, but due to the difference in delay time inside the LSI, the output from the output terminals 91 to 9° of the LSI is not output on the bus lO. A short circuit occurs and a large current flows, causing the LSI
It has the disadvantage of degrading the reliability of the system and causing failure.

SUMMARY OF THE INVENTION An object of the present invention is to provide an LSI output buffer that eliminates the above-mentioned problems.

[Means to solve the problem]

The present invention includes a delay circuit that delays an input signal, an AND circuit that receives signals from the delay circuit and an input terminal, and a NOT circuit that inverts a signal from an output control terminal.

A NAN that receives the signals from the AND circuit and NOT circuit as input.
D circuit, a NOR circuit whose inputs are the signals from the AND circuit and the output control terminal, and whose source is the power supply and whose gate is the NA circuit.
An LSI comprising: a P-channel transistor whose drain is connected to the LSI output terminal in an ND circuit; and an N-channel transistor whose source is connected to the ground, and whose gate is connected to the NOR circuit and to the LSI output terminal. is the output buffer of

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the output buffer of the present invention. an AND circuit 12 which receives as input, a NOT circuit 3 which inverts the signal of the output control terminal 2, and an AND circuit 1.
A NAND circuit 4 receives signals from the AND circuit 12 and the NOT circuit 3 as inputs, a NOR circuit 5 receives signals from the AND circuit 12 and the output control terminal 2, and has a source connected to the power supply terminal 6 and a gate connected to the NAND circuit 4.
The ND circuit 4 includes a P-channel transistor 7 whose drain is connected to the LSI output terminal 9, and an N-channel transistor 8 whose source is grounded and whose gate is connected to the NOR circuit 5 and the drain connected to the LSI output terminal 9. It is.

Since 1 to 9 in FIG. 1 are the same as the conventional output buffer shown in FIG. 2, their explanations will be omitted here.

In FIG. 1, according to the present invention, since the input terminal 1 and the output of the delay circuit 11 are input to the input of the AND circuit 12, the delay circuit 11 and the AND circuit 12 constitute a differentiating circuit. As a result, LSI output terminal 9 has 11
A signal with a narrower width of ' is output.

FIG. 4 shows a time chart when the LSI output terminals of the two output buffers according to the present invention shown in FIG. 1 have a bus structure.As shown in FIG. A signal with a narrower width is output. If the output of each output buffer is controlled during the period T shown in Figure 4, the output from the output buffers of the two LSIs will both be % Oa, and no large current will flow. .

〔Effect of the invention〕

As explained above, the present invention has the advantage that by providing a differential circuit using a delay circuit and an AND circuit at the input terminal of an output buffer, collision of data on the bus can be avoided when the output of an LSI is connected to the bus. There is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of an output buffer according to the present invention, FIG. 2 is a circuit diagram of an embodiment of an output buffer according to the prior art, and FIG. 3 is a circuit diagram of an embodiment of an output buffer according to the present invention. FIG. 4 is a time chart of a circuit example in which the output terminals of two LSIs are connected by a bus. 1...Input terminal 2...Output control terminal 3
...NOT circuit 4...NANt) circuit 5...NOR circuit 6...Power terminal 7
... P channel transistor 8 ... N channel transistor 9 ... LSI output terminal 11 ... Delay circuit 1
2...AND circuit

Claims (1)

[Claims] (1) A delay circuit that delays an input signal, an AND circuit that receives signals from the delay circuit and the input terminal, a NOT circuit that inverts the signal from the output control terminal, and the AND circuit and the N circuit.
A NAND circuit which receives the signal of the OT circuit as input, and the AN
A NOR circuit that receives signals from the D circuit and the output control terminal, a P-channel transistor whose source is connected to the power supply, whose gate is connected to the NAND circuit, and whose drain is connected to the LSI output terminal, and whose source is the ground and whose gate is the NOR circuit. N whose drains are connected to the LSI output terminals, respectively.
An LS characterized by having a channel transistor.
I output buffer.