JPS6393220A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To evade the contention of data between an internal bidirectional buffer of a logic integrated circuit and an external bidirectional buffer by delaying the rise timing of the control signal of the internal bidirectional buffer of the logic integrated circuit by an AND circuit and an input buffer. CONSTITUTION:If an output signal S10 of a direction control circuit C2 is changed from the logical high level to the logical low level at a time T3, a signal S11 goes to the logical low level at a time T3+t3 because an output buffer G6 has a delay t3. During the period from the time T3 to the time T3+t3, an external bidirectional buffer G5 is so directed that data flows in the direction from a signal S7 to a signal S12. An AND circuit G8 sets an output signal S13 to the logical low level after a delay time t5. That is, the signal S13 goes to the logical low level at a time T3+t5, and data of the signal S7 passes a bidirectional buffer G4 and is outputted as a signal S8. In such a case, the delay of the circuit G8 is shorter than that of an output buffer G6, and the time t3 is shorter than the time t5. Therefore, the buffer G5 is orientented to the direction in which the signal S12 is outputted as the signal S7 after the buffer G4 is oriented to the direction in which the signal S7 is outputted as the signal S8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a logic integrated circuit used in various industrial fields.

2. Description of the Related Art With the recent development of microcomputers, various logic integrated circuits have come into use. Conventionally, in logic circuits, many methods have been used to exchange signals in both directions by changing the direction of data on one signal line.

Further, the bidirectional signal lines as described above are often connected in the form of a bus and usually have a large load.

For this reason, if the load driving capability of the bidirectional buffer of the logic integrated circuit is smaller than the required load, the bidirectional buffer is provided outside the logic integrated circuit and used.

The conventional bidirectional buffer 7 control circuit as described above will be explained below with reference to FIG.

FIG. 3 shows the connection between a conventional logic integrated circuit and an external bidirectional buffer.

G1 is a bidirectional buffer inside the logic integrated circuit, and G2 is an external bidirectional buffer provided inside the logic integrated circuit. Further, G3 is an output buffer 7 for outputting a signal for switching the data direction of the external bidirectional buffer G2 to the outside of the logic integrated circuit. C1 is external bidirectional buffer G1 and output buffer y
This is a direction control circuit that generates a direction control signal input to G3.

Sl is bidirectional buffer G1 and external bidirectional buffer yG2e
It is a two-way signal to connect. S2 is a bidirectional signal S1f,
Input data input into the logic integrated circuit through the bidirectional puff 77G1t, and conversely, S3 is output data for outputting data inside the logic integrated circuit as a bidirectional signal S1 through the bidirectional buffer IG1.

S4 is a direction control signal output from the direction control circuit, S5
is an external bidirectional buffer control signal output from the output rose 77G3, and S6 is a bidirectional signal that connects the external bidirectional buffer 7Ci2 to any other circuit.

The operation of the logic integrated circuit and external bidirectional buffer configured as described above will be explained below.

When the output S4 of the direction control circuit C4 becomes a logic level high, the external bidirectional buffer 7 control signal S6 also becomes a logic level high. In this state, output data S3 is output as 81, and this bidirectional signal S1 is output as bidirectional signal S6. That is, the output data S3 is output as the bidirectional signal S6.

Next, when the direction control signal S4 becomes a logic level low, the external bidirectional buffer control signal S6 also becomes a logic level low.

In this state, the bidirectional signal S6 is output as the bidirectional signal S1, and the bidirectional signal S1 is output as the input data S2. That is, the bidirectional signal S6 is input as 82 into the logic integrated circuit.

Furthermore, the operation of the conventional example described above will be explained in detail using the timing chart of FIG.

When the output S4 of the direction control circuit C1 changes from logic level high to low at time T1, the output buffer 7G3
The delay t1 at the time of falling is directed in the direction in which data flows in the direction of the waiting data S2. Therefore, during this period, the bidirectional signal S1 becomes high impedance.

Conversely, the direction control signal 84 changes from logic level low to high
2, the external bidirectional buffer control signal S6 becomes logic high at the time T2+t2 because the output buffer 7G3 has the entire delay t2 at the time of rising.

During this period from T2 to T2+t2, the bidirectional buffer IG1 faces the direction in which data flows from the output data S3 to the bidirectional signal S1, and the external bidirectional buffer 7G2 faces the direction from the bidirectional signal S6 to the bidirectional signal S1. facing the direction in which data flows.

Problems to be Solved by the Invention However, during the period from T2 to T2+t2, data contention may occur on the bidirectional signal S1. And two-way buffer 7G1. There is a possibility that an excessive current may momentarily flow through the elements constituting the external bidirectional buffer G2f, which is undesirable from a practical point of view, as it may cause deterioration of the elements.

A conceivable method for avoiding this data conflict is to independently control the data direction of the bidirectional buffer and the external bidirectional buffer. However, this requires switching the two control signals at different times, which has the disadvantage that the direction control circuit becomes very complex.

In view of the above drawbacks, the present invention provides a logic integrated circuit with a bidirectional buffer 7 control circuit that can avoid data conflicts by only adding one type of signal that determines the data direction of the bidirectional buffer and a small-scale circuit. It is something.

Means for Solving the Problems In order to solve the above problems, the logic integrated circuit of the present invention comprises:
In the conventional example, the external bidirectional buffer control signal is input again into the logic integrated circuit through the input buffer, and the logical product of the output signal of the input cover sofa and the direction control signal output from the direction control circuit is calculated inside the logic integrated circuit. The configuration is such that it is used as a direction control signal for a bidirectional buffer.

Operation: With this configuration, data conflicts can be prevented by delaying the rise timing of the control signal of the bidirectional back 1 inside the logic integrated circuit by the AND circuit and the input buffer 7.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the connection between a logic integrated circuit and an external bidirectional buffer according to an embodiment of the present invention.

G4 is a bidirectional buffer inside the logic integrated circuit, and the data direction of the bidirectional buffer is switched by a control signal S13. G6 is an external bidirectional buffer 7 provided outside the logic integrated circuit. G6 is an external bidirectional buffer control signal S11 that switches the data direction of the external bidirectional buffer G5.
This is an output buffer that outputs the data to the outside of the logic integrated circuit. C7 is an input buffer for inputting S11 for switching the data direction of the external bidirectional buffer G5 from outside to the inside of the logic integrated circuit, and C2 is a direction control circuit that generates a direction control signal. C8 is an AND circuit for taking the logical product of the output of the input buffer 7G7 and the direction control signal which is the output signal of the direction control circuit C2, and inputs the output of the AND circuit as the control signal S13 to the bidirectional buffer G4. Also, S7 is a bidirectional buffer G4 and an external bidirectional buffer 7.
S8 is the input data that inputs the bidirectional signal S7 into the logic integrated circuit through the entire bidirectional buffer G4, and S9 is the input data that bidirectionally connects the data inside the logic integrated circuit to the entire G4. This is output data to be output as a bidirectional signal S7. S10 is a direction control signal output from the direction control circuit C2, and S11 is an external bidirectional buffer control signal output from the output buffer 7Ge. S12 is a bidirectional signal that connects the external bidirectional buffer Gs and any other circuit. Furthermore, S13 is a control signal of G4 outputted from AND circuit G8.

The operation of the logic integrated circuit and external bidirectional buffer configured as described above will be explained below.

When the output S1o of the direction control circuit C2 becomes a low logic level, the logic level of the external bidirectional buffer 7 control signal S11 becomes low through the output back yGe. Therefore, the bidirectional signal S12 is output as the external bidirectional buffer 7G5fjr, S12. Furthermore, since the direction control signal S1o is at a low logic level, the output 313 of the AND circuit G8 is also at a low logic level. Therefore, both signals S7 are output as 53s through the bidirectional buffer IG4. Therefore, when the direction control signal S10 becomes a low logic level, the bidirectional signal S12 is inputted into the logic integrated circuit as input data S8.

Conversely, when the direction control signal S1o becomes a high logic level, it passes through the output bag 77G6i and outputs the external bidirectional buffer control signal S1.
A logic level of 1 is high. Therefore, S7 passes through the external bidirectional buffer 7G5i and is output as 312. Also S
11 becomes a logic level high, the output of the input buffer 7G7 also becomes a logic level high, and the output 313 of the AND circuit G8 becomes
The logic level is also high. In this case, the data of the output data S9 is output to the G-[i- street S7. That is, it is output as data S12 of output data S9.

Further, the operation of the above-mentioned embodiment will be explained in detail using the timing chart shown in FIG.

When the output signal S1o of the direction control circuit C2 changes from logic level high to low at the time T3, the output rose core G
Since S11 has a delay t3' (i-) when 6 falls, the logic level becomes low at the time of T3+t3.
During the period from T3+t3, G5 faces the direction in which data flows from S7 to S12. Also, AND circuit G8
When the direction control circuit S10 becomes a logic level low, the output of the AND circuit G8, S13, becomes a logic level low after the delay time t5 when the fall of the AND circuit G8 reaches 9 o'clock.In other words, S13 becomes a logic level low at the time of T3+t5. Therefore, the data of S7 is output as 04 pSs.

In this case, the delay of the AND circuit inside the logic integrated circuit is usually smaller than the delay of the output buffer. Therefore, t3 is smaller than t6. Therefore, the logic level of the output S13 becomes low faster than the logic level of S11 becomes low, and after the bidirectional back 7G4 is in the direction of outputting as the bidirectional signal s'ylsa, the external bidirectional buffer Gs outputs S12 as S'ylsa.
7 in the direction of output. For this reason, no data conflict can occur in the bidirectional signal S7 before and after T3.

Conversely, when 810 changes from logic level low to high at time T4, S11 becomes logic level high at time T4+t4 because 06 has a delay t4 at the time of rise. Then, from the time of T4+t4, G5 becomes S7'1iS1
The direction is to output as 2.

Further, 313 becomes a logic level high as the output of 08 when S10 and S11 become a logic level high. G7 and 0
If we consider the sum of the delay times at the rise of 8 as t6, then S
13 becomes logic level high at T4+t4+t6. That is, after S11 goes to logic level high, 8
13 becomes a logic level high. Therefore, G5 is 57iS1
After changing the direction to output as 2, G4 outputs S3'iS
It will face the direction of output as 7. Therefore, no data conflict can occur even after leakage of T4.

In this example, the G6. Output buffer as G7,
I used an input buffer, but G6. The control signal of the bidirectional buffer may be fixed to the output side and used as G end.

Effects of the Invention As described above, the present invention achieves avoidance of data conflicts between the internal bidirectional buffer of the logic integrated circuit and the external bidirectional buffer using a simple circuit configuration provided with an input buffer and an AND circuit. .

Furthermore, in the present invention, the load of the control signal input of the external bidirectional buffer connected to this output buffer is uncertain because it depends on the external circuit configuration, and the output buffer delay time may also change accordingly. Regardless of the value of this delay time, a period of conflict avoidance can always be maintained, and its practical effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part of a logic integrated circuit and an external bidirectional buffer in an embodiment of the present invention, FIG. 2 is a timing chart of the same, and FIG. 3 is a main part of a conventional logic integrated circuit and an external bidirectional buffer. The circuit diagram and FIG. 4 are the same timing chart. G4...Bidirectional buffer, G5...External bidirectional buffer, G6...Output buffer 7, G
7...Input buffer 7゜Name of agent Patent attorney Toshio Nakao and 1 other person 4th
figure

Claims (1)

[Claims] a bidirectional buffer on the same chip, and a direction control circuit for switching the data direction of the bidirectional buffer and the chip external bidirectional buffer connected to the bidirectional buffer;
an output buffer for outputting the direction control signal output from the direction control circuit to the outside of the chip; an input buffer for inputting the output signal of the output buffer into the inside of the chip; and an output signal of the input buffer and the direction. An AND circuit is provided for taking a logical product of the control signals, and the AND circuit is provided.
A logic integrated circuit characterized in that an output signal of the circuit is a data direction control signal of the bidirectional buffer.