JPS56118107A - Sequence controller - Google Patents
Sequence controllerInfo
- Publication number
- JPS56118107A JPS56118107A JP2143880A JP2143880A JPS56118107A JP S56118107 A JPS56118107 A JP S56118107A JP 2143880 A JP2143880 A JP 2143880A JP 2143880 A JP2143880 A JP 2143880A JP S56118107 A JPS56118107 A JP S56118107A
- Authority
- JP
- Japan
- Prior art keywords
- external
- set value
- section
- setter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1162—Forcing I-O
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/15—Plc structure of the system
- G05B2219/15049—Timer, counter, clock-calendar, flip-flop as peripheral
Abstract
PURPOSE:To enable to change the set value even if the sequence controller is in operation, by externally locating the external setter group outside the sequence controller. CONSTITUTION:A set value data signal 3b' is included in the sequence instruction 2a' read out from a program memory 2, it is inputted to an operation section 3, from which input is made to a set value selection section 7 and an external set readout section 10. The external set readout section 10 outputs the setter readout signal 10a as the address signal to the external setter group 9 according to the set value data 3b', only when the selection signal 3c is the signal selecting the specified setter of the external setter group 9. The set value selection section 7 selects either internal set value data 3b' or external data 8a, and transmits it as the set data 7a of the timer or counter to a timer and counter control section 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2143880A JPS56118107A (en) | 1980-02-22 | 1980-02-22 | Sequence controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2143880A JPS56118107A (en) | 1980-02-22 | 1980-02-22 | Sequence controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56118107A true JPS56118107A (en) | 1981-09-17 |
Family
ID=12054966
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2143880A Pending JPS56118107A (en) | 1980-02-22 | 1980-02-22 | Sequence controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56118107A (en) |
-
1980
- 1980-02-22 JP JP2143880A patent/JPS56118107A/en active Pending
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