JPS5734359A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5734359A
JPS5734359A JP10891680A JP10891680A JPS5734359A JP S5734359 A JPS5734359 A JP S5734359A JP 10891680 A JP10891680 A JP 10891680A JP 10891680 A JP10891680 A JP 10891680A JP S5734359 A JPS5734359 A JP S5734359A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline
wiring
diode
aperture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10891680A
Other languages
Japanese (ja)
Inventor
Shigeru Komatsu
Michio Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10891680A priority Critical patent/JPS5734359A/en
Publication of JPS5734359A publication Critical patent/JPS5734359A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To easily control the characteristics of the polycrystalline Si layer as well as to obtain high integration for the subject semiconductor device by a method wherein a device having a resistor, consisting of polycrystalline Si, a wiring, a diode and the like, is formed by the aid of a self-aligning method using an Si nitriding film, for example. CONSTITUTION:The polycrystalline Si layer 5 is formed on the selective oxide film 4 provided on an N type Si substrate 1, for example. High density of impurities are induced when the layer is turned to a wiring. Then, after an oxide film 6 is provided on the surface, a base layer 7 is formed by implanting B. When the layer 6 is turned to a resistance element, the B is additionally implanted so as to obtain the prescribed layer resistance by providing a resist mask. Then, for example, after a nitriding film mask 8 is formed and an emitter layer 11 is formed by injection (an aperture is provided on the layer 6 and a junction is formed when a diode is provided), an aperture is provided on the connected section, an electrode and a wiring are formed and used as a circuit. Thus, a high integration can be obtained by performing a self-alignment and, at the same time, the control of characteristics of the element, wherein polycrystalline layer is used, can be peroformed easily.
JP10891680A 1980-08-08 1980-08-08 Semiconductor device and manufacture thereof Pending JPS5734359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10891680A JPS5734359A (en) 1980-08-08 1980-08-08 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10891680A JPS5734359A (en) 1980-08-08 1980-08-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5734359A true JPS5734359A (en) 1982-02-24

Family

ID=14496891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10891680A Pending JPS5734359A (en) 1980-08-08 1980-08-08 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5734359A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5488085A (en) * 1977-12-26 1979-07-12 Toshiba Corp Nanufacture for semiconductor device
JPS5596653A (en) * 1979-01-15 1980-07-23 Philips Nv Semiconductor device and method of fabricating same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5488085A (en) * 1977-12-26 1979-07-12 Toshiba Corp Nanufacture for semiconductor device
JPS5596653A (en) * 1979-01-15 1980-07-23 Philips Nv Semiconductor device and method of fabricating same

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