JPS5730181A - Control system for buffer invalidation - Google Patents
Control system for buffer invalidationInfo
- Publication number
- JPS5730181A JPS5730181A JP10470380A JP10470380A JPS5730181A JP S5730181 A JPS5730181 A JP S5730181A JP 10470380 A JP10470380 A JP 10470380A JP 10470380 A JP10470380 A JP 10470380A JP S5730181 A JPS5730181 A JP S5730181A
- Authority
- JP
- Japan
- Prior art keywords
- address
- access request
- buffer invalidation
- buffer
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
Abstract
PURPOSE:To improve the processing efficiency of an information processing system by decreasing the frequency of buffer invalidating processing. CONSTITUTION:Checks on whether the address of an access request coincides with the contents of address preserving ports 10-0-10-3 or not are made and when one address preserving port has a coincident address, the AND conditions of a gate A2 are not satisfied by a signal BIA0 or BIA3, so that even if the access request is for writing operation, a buffer invalidation request is not sent out. When none of the ports 10-0-10-3 has the contents coinciding with the address of the access request and the access request is for the writing operation, the address is set to the port which corresponds to the access request origin and a buffer invalidation request and a buffer invalidation address are sent to the processor of the origin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10470380A JPS5730181A (en) | 1980-07-29 | 1980-07-29 | Control system for buffer invalidation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10470380A JPS5730181A (en) | 1980-07-29 | 1980-07-29 | Control system for buffer invalidation |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5730181A true JPS5730181A (en) | 1982-02-18 |
Family
ID=14387834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10470380A Pending JPS5730181A (en) | 1980-07-29 | 1980-07-29 | Control system for buffer invalidation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5730181A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02133626A (en) * | 1988-11-10 | 1990-05-22 | Toray Ind Inc | Fluff yarn having different color effect |
-
1980
- 1980-07-29 JP JP10470380A patent/JPS5730181A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02133626A (en) * | 1988-11-10 | 1990-05-22 | Toray Ind Inc | Fluff yarn having different color effect |
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