JPS572554A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS572554A
JPS572554A JP7547280A JP7547280A JPS572554A JP S572554 A JPS572554 A JP S572554A JP 7547280 A JP7547280 A JP 7547280A JP 7547280 A JP7547280 A JP 7547280A JP S572554 A JPS572554 A JP S572554A
Authority
JP
Japan
Prior art keywords
resin
releasing agent
layer
mold
molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7547280A
Other languages
Japanese (ja)
Inventor
Kenji Miyajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7547280A priority Critical patent/JPS572554A/en
Publication of JPS572554A publication Critical patent/JPS572554A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To perform a resin sealing of a semiconductor device with good adherence and good mold releasability by covering the surface of a semiconductor element with the first resin molding layer containing no mold releasing agent and laminating the second molding layer containing mold releasing agent to form a resin-sealed enclosure. CONSTITUTION:In a resin-sealed type semiconductor device, a semiconductor element 3 associated with a lead frame and wire bonded is inserted into a lower die of a resin mold, and the first molding resin layer 20a is formed and covered with molding resin containing no mold releasing agent. The second molding resin layer 20b is formed with molding resin containing mold releasing agent, and a resin-sealed enclosure is formed with these two layers. Since the first layer covered on the semiconductor element does not contain the mold releasing agent in this manner, it has good adherence, while since the second layer of the surface layer of the enclosure contains the mold releasing agent, it can be readily isolated from the mold.
JP7547280A 1980-06-06 1980-06-06 Semiconductor device Pending JPS572554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7547280A JPS572554A (en) 1980-06-06 1980-06-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7547280A JPS572554A (en) 1980-06-06 1980-06-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS572554A true JPS572554A (en) 1982-01-07

Family

ID=13577274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7547280A Pending JPS572554A (en) 1980-06-06 1980-06-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS572554A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005026447A (en) * 2003-07-02 2005-01-27 Sumitomo Bakelite Co Ltd Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005026447A (en) * 2003-07-02 2005-01-27 Sumitomo Bakelite Co Ltd Semiconductor device and method of manufacturing the same

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