JPS5723157A - Memory address system of microprocessor - Google Patents

Memory address system of microprocessor

Info

Publication number
JPS5723157A
JPS5723157A JP9711580A JP9711580A JPS5723157A JP S5723157 A JPS5723157 A JP S5723157A JP 9711580 A JP9711580 A JP 9711580A JP 9711580 A JP9711580 A JP 9711580A JP S5723157 A JPS5723157 A JP S5723157A
Authority
JP
Japan
Prior art keywords
bit
selecting
port
microprocessor
memory address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9711580A
Other languages
Japanese (ja)
Inventor
Hiroo Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP9711580A priority Critical patent/JPS5723157A/en
Publication of JPS5723157A publication Critical patent/JPS5723157A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

Abstract

PURPOSE:To read and write a memory continuously by selecting a port according to the contents of the most significant digit bit of an address terminal and by selecting one of memory segments. CONSTITUTION:Four-bit data, eight-bit addresses and two--three-bit control information are inputted to ports 6 and 7, and the four-bit data are set by an input- output instruction. Thus, the addresses are sent to a data bus 4 by the input-output instruction. The outputs of the ports 6 and 7 are inputted to a selector 8, which selects the port 6 when the most significant digit bit MSB of an address bus 3 is a ''0'', or selects the port 7 when it is ''1''. Four bits of the selector's output are decoded by a decoder 9 into a signal for selecting one of memory segments.
JP9711580A 1980-07-16 1980-07-16 Memory address system of microprocessor Pending JPS5723157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9711580A JPS5723157A (en) 1980-07-16 1980-07-16 Memory address system of microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9711580A JPS5723157A (en) 1980-07-16 1980-07-16 Memory address system of microprocessor

Publications (1)

Publication Number Publication Date
JPS5723157A true JPS5723157A (en) 1982-02-06

Family

ID=14183566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9711580A Pending JPS5723157A (en) 1980-07-16 1980-07-16 Memory address system of microprocessor

Country Status (1)

Country Link
JP (1) JPS5723157A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6414648A (en) * 1987-07-08 1989-01-18 Mitsubishi Electric Corp Arithmetic processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6414648A (en) * 1987-07-08 1989-01-18 Mitsubishi Electric Corp Arithmetic processor

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