JPS57212698A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS57212698A
JPS57212698A JP56097748A JP9774881A JPS57212698A JP S57212698 A JPS57212698 A JP S57212698A JP 56097748 A JP56097748 A JP 56097748A JP 9774881 A JP9774881 A JP 9774881A JP S57212698 A JPS57212698 A JP S57212698A
Authority
JP
Japan
Prior art keywords
error
data
signal
register
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56097748A
Other languages
Japanese (ja)
Inventor
Toshio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56097748A priority Critical patent/JPS57212698A/en
Publication of JPS57212698A publication Critical patent/JPS57212698A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To receive next cycle data only when an error occurs, by controlling the reception of data through a holding circuit which respectively holds an error signal reception state and the state of a control signal to a register to which data is transferred. CONSTITUTION:If data transferred from a storage device 1 to a register 10 has an error, the error detecting and correcting circuit 3 of the device 1 generates an error detection signal, and an FF4 whose operation timing is controlled by a clock holds the state wherein the error signal is received and closes an AND gate 6. Consequently, the setting signal B of the register 10 is intercepted and at the same time, an FF5 holds the state of a signal B. Hold outputs of FF 5 and 6 are applied through an AND gate 7, an OR gate 8, and an AND gate 9 opened by a next clock to the register 10, which receives transferred data after the error is corrected by the circuit 3. Therefore, transfer information is received in a next cycle only when an error occurs, so that the data transfer system proves a high processing speed.
JP56097748A 1981-06-23 1981-06-23 Data transfer system Pending JPS57212698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56097748A JPS57212698A (en) 1981-06-23 1981-06-23 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56097748A JPS57212698A (en) 1981-06-23 1981-06-23 Data transfer system

Publications (1)

Publication Number Publication Date
JPS57212698A true JPS57212698A (en) 1982-12-27

Family

ID=14200501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56097748A Pending JPS57212698A (en) 1981-06-23 1981-06-23 Data transfer system

Country Status (1)

Country Link
JP (1) JPS57212698A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165300A (en) * 1983-03-10 1984-09-18 Fujitsu Ltd Memory fault correcting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165300A (en) * 1983-03-10 1984-09-18 Fujitsu Ltd Memory fault correcting system

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