JPS57181136A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57181136A
JPS57181136A JP6647581A JP6647581A JPS57181136A JP S57181136 A JPS57181136 A JP S57181136A JP 6647581 A JP6647581 A JP 6647581A JP 6647581 A JP6647581 A JP 6647581A JP S57181136 A JPS57181136 A JP S57181136A
Authority
JP
Japan
Prior art keywords
film
mask
substrate
micro
miniaturized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6647581A
Other languages
Japanese (ja)
Other versions
JPS6059737B2 (en
Inventor
Satoru Maeda
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6647581A priority Critical patent/JPS6059737B2/en
Priority to US06/307,877 priority patent/US4560421A/en
Publication of JPS57181136A publication Critical patent/JPS57181136A/en
Publication of JPS6059737B2 publication Critical patent/JPS6059737B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To form an element separating region being micro-miniaturized by shaping a mask for an opening section by implanting ions to a selective etching film while forming an inversion preventive layer by implanting ions through the film and an insulating film. CONSTITUTION:The inversion preventive layer 15 is shaped by implanting boron, etc. into a semiconductor substrate 11 while using a resist pattern 14 as a mask from the upper section of an insulating layer 12 and an Al film, etc. 13 molded onto the substrate, and voltage is lowered and boron ions are inplanted in the Al film 13 and etching resisting property is produced. The mask 14 and the film 13 just under the mask are removed, the insulating layer 12 is etched employing the remaining Al film, etc. 13' as masks, an element forming region is opened onto the substrate in self-matching manner, and a source 19, a drain 20, a gate electrode 18, etc. are formed through a normal method. Accordingly, the micro-miniaturized element separating region with no bird-beak is shaped through a process being simplified, and the high degree of integration, etc. can be attained.
JP6647581A 1980-10-02 1981-05-01 Manufacturing method of semiconductor device Expired JPS6059737B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP6647581A JPS6059737B2 (en) 1981-05-01 1981-05-01 Manufacturing method of semiconductor device
US06/307,877 US4560421A (en) 1980-10-02 1981-10-02 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6647581A JPS6059737B2 (en) 1981-05-01 1981-05-01 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57181136A true JPS57181136A (en) 1982-11-08
JPS6059737B2 JPS6059737B2 (en) 1985-12-26

Family

ID=13316838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6647581A Expired JPS6059737B2 (en) 1980-10-02 1981-05-01 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6059737B2 (en)

Also Published As

Publication number Publication date
JPS6059737B2 (en) 1985-12-26

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