JPS57170571A - Manufacture of mos type semiconductor device - Google Patents
Manufacture of mos type semiconductor deviceInfo
- Publication number
- JPS57170571A JPS57170571A JP5587581A JP5587581A JPS57170571A JP S57170571 A JPS57170571 A JP S57170571A JP 5587581 A JP5587581 A JP 5587581A JP 5587581 A JP5587581 A JP 5587581A JP S57170571 A JPS57170571 A JP S57170571A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- gate
- drain
- source
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 6
- 229920005591 polysilicon Polymers 0.000 abstract 6
- 238000005530 etching Methods 0.000 abstract 2
- 230000004913 activation Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To prevent the disconnection of a wire on a polysilicon and to reduce the superposition capacity between a gate, source and a drain by etching the side surface of the polysilicon after an ion implantation with two-layer mask of a mask material and a polysilicon layer. CONSTITUTION:A gate oxidized film 12 and a doped polysilicon 13 are laminated on a P type Si substrate 11, a resist mask 14 is covered, and a sputter etching is performed. Subsequently, with the resist 14 and the polysilicon 13 as masks P ions are implanted to form a source 15 and a drain 16. When an activation and depression are performed, the gate 13 extends downwardly in the amount corresponding to approx. (0.6-0.64)xj with respect to the depth xj. Then, when the vertical side surface of the polysilicon 13 is etched, a taper is produced due to the presence of the impurity density difference. When the etching amount at the lowermost end of the gate 13 is selected to (0.55-0.6)xj, the superposition of the gate 13 and the source 15, the drain 16 becomes approx. zero, the capacity becomes ultrafine, thereby accelerating the operation, and the disconnection can be prevented by the taper.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5587581A JPS57170571A (en) | 1981-04-14 | 1981-04-14 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5587581A JPS57170571A (en) | 1981-04-14 | 1981-04-14 | Manufacture of mos type semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57170571A true JPS57170571A (en) | 1982-10-20 |
JPH024133B2 JPH024133B2 (en) | 1990-01-26 |
Family
ID=13011264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5587581A Granted JPS57170571A (en) | 1981-04-14 | 1981-04-14 | Manufacture of mos type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57170571A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6335290B1 (en) | 1998-07-31 | 2002-01-01 | Fujitsu Limited | Etching method, thin film transistor matrix substrate, and its manufacture |
US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
KR100333155B1 (en) * | 1994-09-16 | 2002-11-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Thin film semiconductor device and manufacturing method |
US6964890B1 (en) | 1992-03-17 | 2005-11-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
-
1981
- 1981-04-14 JP JP5587581A patent/JPS57170571A/en active Granted
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6964890B1 (en) | 1992-03-17 | 2005-11-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
US6984551B2 (en) | 1993-01-18 | 2006-01-10 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
US7351624B2 (en) | 1993-01-18 | 2008-04-01 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
KR100333155B1 (en) * | 1994-09-16 | 2002-11-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Thin film semiconductor device and manufacturing method |
US6335290B1 (en) | 1998-07-31 | 2002-01-01 | Fujitsu Limited | Etching method, thin film transistor matrix substrate, and its manufacture |
KR100349562B1 (en) * | 1998-07-31 | 2002-08-21 | 후지쯔 가부시끼가이샤 | Etching method, thin film transistor matrix substrate, and its manufacture |
US6534789B2 (en) | 1998-07-31 | 2003-03-18 | Fujitsu Limited | Thin film transistor matrix having TFT with LDD regions |
Also Published As
Publication number | Publication date |
---|---|
JPH024133B2 (en) | 1990-01-26 |
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