JPS57178360A - Multilayer structure semiconductor device - Google Patents

Multilayer structure semiconductor device

Info

Publication number
JPS57178360A
JPS57178360A JP6501881A JP6501881A JPS57178360A JP S57178360 A JPS57178360 A JP S57178360A JP 6501881 A JP6501881 A JP 6501881A JP 6501881 A JP6501881 A JP 6501881A JP S57178360 A JPS57178360 A JP S57178360A
Authority
JP
Japan
Prior art keywords
crystal group
semiconductor device
grating constant
belongs
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6501881A
Other languages
English (en)
Inventor
Shinichiro Takasu
Yoshiaki Matsushita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6501881A priority Critical patent/JPS57178360A/ja
Publication of JPS57178360A publication Critical patent/JPS57178360A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
JP6501881A 1981-04-28 1981-04-28 Multilayer structure semiconductor device Pending JPS57178360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6501881A JPS57178360A (en) 1981-04-28 1981-04-28 Multilayer structure semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6501881A JPS57178360A (en) 1981-04-28 1981-04-28 Multilayer structure semiconductor device

Publications (1)

Publication Number Publication Date
JPS57178360A true JPS57178360A (en) 1982-11-02

Family

ID=13274810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6501881A Pending JPS57178360A (en) 1981-04-28 1981-04-28 Multilayer structure semiconductor device

Country Status (1)

Country Link
JP (1) JPS57178360A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479297A (en) * 1981-06-22 1984-10-30 Tokyo Shibaura Denki Kabushiki Kaisha Method of fabricating three-dimensional semiconductor devices utilizing CeO2 and ion-implantation.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479297A (en) * 1981-06-22 1984-10-30 Tokyo Shibaura Denki Kabushiki Kaisha Method of fabricating three-dimensional semiconductor devices utilizing CeO2 and ion-implantation.

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