JPS5717138A - Resin sealing device for semiconductor device - Google Patents

Resin sealing device for semiconductor device

Info

Publication number
JPS5717138A
JPS5717138A JP9252580A JP9252580A JPS5717138A JP S5717138 A JPS5717138 A JP S5717138A JP 9252580 A JP9252580 A JP 9252580A JP 9252580 A JP9252580 A JP 9252580A JP S5717138 A JPS5717138 A JP S5717138A
Authority
JP
Japan
Prior art keywords
semiconductor element
lead frame
resin sealing
metal wire
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9252580A
Other languages
Japanese (ja)
Inventor
Naoto Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP9252580A priority Critical patent/JPS5717138A/en
Publication of JPS5717138A publication Critical patent/JPS5717138A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce generation of defective products by a method wherein the direction of a semiconductor element and a lead frame is reversed to each other. CONSTITUTION:The semiconductor element 2 and the lead frame 1 are connected by a metal wire 3 and they are inserted in the cavity section of the lower metal mold 15 facing downward, the upper metal mold 14 is placed and then resin 16 is poured in. Through these procedures, the contact of the lead frame 1 with an island section and sticking of foreign substances on the surface of the semiconductor element can be prevented due to the sagging of the metal wire, thereby enabling to improve the production rate of nondefective products.
JP9252580A 1980-07-07 1980-07-07 Resin sealing device for semiconductor device Pending JPS5717138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9252580A JPS5717138A (en) 1980-07-07 1980-07-07 Resin sealing device for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9252580A JPS5717138A (en) 1980-07-07 1980-07-07 Resin sealing device for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5717138A true JPS5717138A (en) 1982-01-28

Family

ID=14056753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9252580A Pending JPS5717138A (en) 1980-07-07 1980-07-07 Resin sealing device for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5717138A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6198846A (en) * 1984-10-19 1986-05-17 住友金属鉱山株式会社 Light weight composite panel for building material
US5134773A (en) * 1989-05-26 1992-08-04 Gerard Lemaire Method for making a credit card containing a microprocessor chip
CN105990297A (en) * 2015-01-28 2016-10-05 苏州普福斯信息科技有限公司 Structure of using incoordinate die cavity to cooperate non-sinking wire frame

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6198846A (en) * 1984-10-19 1986-05-17 住友金属鉱山株式会社 Light weight composite panel for building material
US5134773A (en) * 1989-05-26 1992-08-04 Gerard Lemaire Method for making a credit card containing a microprocessor chip
CN105990297A (en) * 2015-01-28 2016-10-05 苏州普福斯信息科技有限公司 Structure of using incoordinate die cavity to cooperate non-sinking wire frame

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