JPS57168536A - Data storing device - Google Patents
Data storing deviceInfo
- Publication number
- JPS57168536A JPS57168536A JP56048604A JP4860481A JPS57168536A JP S57168536 A JPS57168536 A JP S57168536A JP 56048604 A JP56048604 A JP 56048604A JP 4860481 A JP4860481 A JP 4860481A JP S57168536 A JPS57168536 A JP S57168536A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- internal information
- circuit
- information
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/45—Transmitting circuits; Receiving circuits using electronic distributors
Abstract
PURPOSE:To increase the processing speed of information, by detecting both the starting and ending points of received data and analyzing the internal information between these two points to then store the information into a memory. CONSTITUTION:The starting point of continuous binary data, i.e., the output of a receiver is detected by a comparator 223A, and the coincidence signal 22A is delivered. Thus a controlling circuit 26 connects a path switching circuit 23 to an input 23A and stores the internal information transmitted after the starting point data into a serial memory 24A. Then the internal information is shifted successively to the memory 24A. When the internal information equivalent to n bytes is stored, the circuit 26 writes the above-mentioned n byte binary series in parallel into a memory 25. Then the circuit 23 is connected to an input 23B and stores the following n byte binary series is stored in a shift memory 24B. Such operation is repetitively carried out to store the received internal information into the memory 25 with no overlap nor deletion. Then the circuit 26 completes the storing of the internal information into the memory 25 when the ending point coincidence signal is delivered from a comparator 23B.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56048604A JPS57168536A (en) | 1981-03-31 | 1981-03-31 | Data storing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56048604A JPS57168536A (en) | 1981-03-31 | 1981-03-31 | Data storing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57168536A true JPS57168536A (en) | 1982-10-16 |
JPS632386B2 JPS632386B2 (en) | 1988-01-19 |
Family
ID=12808007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56048604A Granted JPS57168536A (en) | 1981-03-31 | 1981-03-31 | Data storing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57168536A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5371856A (en) * | 1990-12-20 | 1994-12-06 | Fujitsu Limited | Transfer data storage system |
-
1981
- 1981-03-31 JP JP56048604A patent/JPS57168536A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5371856A (en) * | 1990-12-20 | 1994-12-06 | Fujitsu Limited | Transfer data storage system |
Also Published As
Publication number | Publication date |
---|---|
JPS632386B2 (en) | 1988-01-19 |
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