JPS57162470A - Non-volatile memory using semiconductor compound - Google Patents

Non-volatile memory using semiconductor compound

Info

Publication number
JPS57162470A
JPS57162470A JP56048853A JP4885381A JPS57162470A JP S57162470 A JPS57162470 A JP S57162470A JP 56048853 A JP56048853 A JP 56048853A JP 4885381 A JP4885381 A JP 4885381A JP S57162470 A JPS57162470 A JP S57162470A
Authority
JP
Japan
Prior art keywords
layer
insulating film
substrate
electrode
type gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56048853A
Other languages
Japanese (ja)
Other versions
JPH0235471B2 (en
Inventor
Tatsuhiko Niina
Takao Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP56048853A priority Critical patent/JPS57162470A/en
Publication of JPS57162470A publication Critical patent/JPS57162470A/en
Publication of JPH0235471B2 publication Critical patent/JPH0235471B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To manufacture the non-volatile memory operating at high speed by a method wherein the hetero joint comprising the non-dope GaAs layer and the N type GaAs layer is used as the electronic storage layer. CONSTITUTION:The N type GaAs layer 11 with several mum thcikness and the non-voltile GaAs layer 12 with less thickness of 50-1,000Angstrom are laminated on the N type GaAs substrate 10 to be epitaxially grown. Then the first insulating film 14 with around 200Angstrom thickness is mounted on the central part of said layer 12 and the floating gate 14 comprising Mo or multicrystal Si with less dimension is formed on said insulating film 14 and the exposed surface of the film 14 is surrounded by the second insulating film 15 whereon the gate electrode 16 is mounted. Then the source electrode 17 and the drain electrode 18 are respectively formed on the layer 12 holding the gate 13 while the reverse side of the substrate 10 is also coated with the substrate electrode 19. Through these procedures, the electronic storage layer is consistued by means of the hetero joint with the said layer 11 making use of said thinner layer 12 as the operating layer.
JP56048853A 1981-03-31 1981-03-31 Non-volatile memory using semiconductor compound Granted JPS57162470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56048853A JPS57162470A (en) 1981-03-31 1981-03-31 Non-volatile memory using semiconductor compound

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56048853A JPS57162470A (en) 1981-03-31 1981-03-31 Non-volatile memory using semiconductor compound

Publications (2)

Publication Number Publication Date
JPS57162470A true JPS57162470A (en) 1982-10-06
JPH0235471B2 JPH0235471B2 (en) 1990-08-10

Family

ID=12814819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56048853A Granted JPS57162470A (en) 1981-03-31 1981-03-31 Non-volatile memory using semiconductor compound

Country Status (1)

Country Link
JP (1) JPS57162470A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0817278A2 (en) * 1996-06-28 1998-01-07 Siemens Aktiengesellschaft Memory cell

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0817278A2 (en) * 1996-06-28 1998-01-07 Siemens Aktiengesellschaft Memory cell
EP0817278A3 (en) * 1996-06-28 1998-01-28 Siemens Aktiengesellschaft Memory cell

Also Published As

Publication number Publication date
JPH0235471B2 (en) 1990-08-10

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