JPS5715274A - Buffer storage control system - Google Patents

Buffer storage control system

Info

Publication number
JPS5715274A
JPS5715274A JP8864980A JP8864980A JPS5715274A JP S5715274 A JPS5715274 A JP S5715274A JP 8864980 A JP8864980 A JP 8864980A JP 8864980 A JP8864980 A JP 8864980A JP S5715274 A JPS5715274 A JP S5715274A
Authority
JP
Japan
Prior art keywords
block
replacement
information
bit
inhibition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8864980A
Other languages
Japanese (ja)
Inventor
Hidekiyo Ozawa
Shigeru Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8864980A priority Critical patent/JPS5715274A/en
Publication of JPS5715274A publication Critical patent/JPS5715274A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To inhibit the dynamic expelling operation of a buffer memory device by providing a bit for inhibiting expulsion from the buffer memory device and a circuit which resets the bit on the basis of replacement information. CONSTITUTION:A storage part for data sent, block by block, from a main storage device and a tag part 1 having a storage area for information on addresses of data stored in the main storage device are provided, and an area for inhibition replacement information bits is added to a replacement information storing circuit 4. Then, a generating and erasing circuit 12 for inhibition/replacement bit information and a replacement determining circuit 9 which determines a block to be expelled on the basis of the replacement information and inhibition/replacement bit information when no block to be access resides in the memory device are provided; data belonging to a predetermined address area are excluded from the block to be expelled and when some block is to be expelled continuously at a prescribed frequency, its expulsion is canceled.
JP8864980A 1980-06-30 1980-06-30 Buffer storage control system Pending JPS5715274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8864980A JPS5715274A (en) 1980-06-30 1980-06-30 Buffer storage control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8864980A JPS5715274A (en) 1980-06-30 1980-06-30 Buffer storage control system

Publications (1)

Publication Number Publication Date
JPS5715274A true JPS5715274A (en) 1982-01-26

Family

ID=13948657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8864980A Pending JPS5715274A (en) 1980-06-30 1980-06-30 Buffer storage control system

Country Status (1)

Country Link
JP (1) JPS5715274A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8261022B2 (en) 2001-10-09 2012-09-04 Agere Systems Inc. Method and apparatus for adaptive cache frame locking and unlocking

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8261022B2 (en) 2001-10-09 2012-09-04 Agere Systems Inc. Method and apparatus for adaptive cache frame locking and unlocking
US8478944B2 (en) 2001-10-09 2013-07-02 Agere Systems Llc Method and apparatus for adaptive cache frame locking and unlocking

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