JPS57162168A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS57162168A
JPS57162168A JP56047781A JP4778181A JPS57162168A JP S57162168 A JPS57162168 A JP S57162168A JP 56047781 A JP56047781 A JP 56047781A JP 4778181 A JP4778181 A JP 4778181A JP S57162168 A JPS57162168 A JP S57162168A
Authority
JP
Japan
Prior art keywords
moving
block
bit information
change bit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56047781A
Other languages
Japanese (ja)
Other versions
JPS612978B2 (en
Inventor
Masanori Takahashi
Minoru Etsuno
Akira Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56047781A priority Critical patent/JPS57162168A/en
Publication of JPS57162168A publication Critical patent/JPS57162168A/en
Publication of JPS612978B2 publication Critical patent/JPS612978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To avoid ineffective data from moving out, by discriminating if moving-out to a main storage is to be done or not through a logical product between an effective bit of a block and a change bit. CONSTITUTION:The content of a way block corresponding to a replacement objective block of a swap system buffer memory tag section 1 is selected at a selection circuit 21 and set to a move-out register 15. A move-out logical circuit 6 discriminates if moving-out of the replacement objective block is done to the main storage based on the valid bit information of the selected way block and the change bit information set already in a change bit register 16. The circuit 6 decides the moving-out only when the valid bit information is effective and the change bit information is changed.
JP56047781A 1981-03-30 1981-03-30 Memory access control system Granted JPS57162168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047781A JPS57162168A (en) 1981-03-30 1981-03-30 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047781A JPS57162168A (en) 1981-03-30 1981-03-30 Memory access control system

Publications (2)

Publication Number Publication Date
JPS57162168A true JPS57162168A (en) 1982-10-05
JPS612978B2 JPS612978B2 (en) 1986-01-29

Family

ID=12784908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047781A Granted JPS57162168A (en) 1981-03-30 1981-03-30 Memory access control system

Country Status (1)

Country Link
JP (1) JPS57162168A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263350A (en) * 1985-06-28 1987-03-20 Yokogawa Hewlett Packard Ltd Information processor equipped with cache memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137287U (en) * 1988-03-04 1989-09-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263350A (en) * 1985-06-28 1987-03-20 Yokogawa Hewlett Packard Ltd Information processor equipped with cache memory

Also Published As

Publication number Publication date
JPS612978B2 (en) 1986-01-29

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