JPS57152046A - Instruction buffer controlling method - Google Patents

Instruction buffer controlling method

Info

Publication number
JPS57152046A
JPS57152046A JP56036325A JP3632581A JPS57152046A JP S57152046 A JPS57152046 A JP S57152046A JP 56036325 A JP56036325 A JP 56036325A JP 3632581 A JP3632581 A JP 3632581A JP S57152046 A JPS57152046 A JP S57152046A
Authority
JP
Japan
Prior art keywords
instruction
pointer
setting
numeral
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56036325A
Other languages
English (en)
Other versions
JPS6211736B2 (ja
Inventor
Takahide Oogami
Yasushi Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56036325A priority Critical patent/JPS57152046A/ja
Publication of JPS57152046A publication Critical patent/JPS57152046A/ja
Publication of JPS6211736B2 publication Critical patent/JPS6211736B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56036325A 1981-03-13 1981-03-13 Instruction buffer controlling method Granted JPS57152046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56036325A JPS57152046A (en) 1981-03-13 1981-03-13 Instruction buffer controlling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56036325A JPS57152046A (en) 1981-03-13 1981-03-13 Instruction buffer controlling method

Publications (2)

Publication Number Publication Date
JPS57152046A true JPS57152046A (en) 1982-09-20
JPS6211736B2 JPS6211736B2 (ja) 1987-03-14

Family

ID=12466680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56036325A Granted JPS57152046A (en) 1981-03-13 1981-03-13 Instruction buffer controlling method

Country Status (1)

Country Link
JP (1) JPS57152046A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6133545A (ja) * 1984-07-26 1986-02-17 Nec Corp デ−タ処理装置
JPH0329027A (ja) * 1989-06-27 1991-02-07 Matsushita Electric Ind Co Ltd 命令バッファ装置を有するデータ処理装置
JPH04369038A (ja) * 1991-06-18 1992-12-21 Matsushita Electric Ind Co Ltd 命令プリフェッチ装置
JPH052484A (ja) * 1991-06-24 1993-01-08 Mitsubishi Electric Corp スーパースカラプロセツサ
JPH05197545A (ja) * 1991-12-10 1993-08-06 Mitsubishi Electric Corp マイクロコンピュータ
WO1995016954A1 (fr) * 1993-12-15 1995-06-22 Silicon Graphics Inc. Circuit de traitement d'instructions dans un systeme informatique
JPH10510146A (ja) * 1994-11-21 1998-10-06 ザ ユニバーシティ オブ リーズ 改変されたプロテイナーゼインヒビター

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6133545A (ja) * 1984-07-26 1986-02-17 Nec Corp デ−タ処理装置
JPH0329027A (ja) * 1989-06-27 1991-02-07 Matsushita Electric Ind Co Ltd 命令バッファ装置を有するデータ処理装置
JPH04369038A (ja) * 1991-06-18 1992-12-21 Matsushita Electric Ind Co Ltd 命令プリフェッチ装置
JPH052484A (ja) * 1991-06-24 1993-01-08 Mitsubishi Electric Corp スーパースカラプロセツサ
JPH05197545A (ja) * 1991-12-10 1993-08-06 Mitsubishi Electric Corp マイクロコンピュータ
WO1995016954A1 (fr) * 1993-12-15 1995-06-22 Silicon Graphics Inc. Circuit de traitement d'instructions dans un systeme informatique
US5954815A (en) * 1993-12-15 1999-09-21 Silicon Graphics, Inc. Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address
US6247124B1 (en) 1993-12-15 2001-06-12 Mips Technologies, Inc. Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions
US6691221B2 (en) 1993-12-15 2004-02-10 Mips Technologies, Inc. Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution
JPH10510146A (ja) * 1994-11-21 1998-10-06 ザ ユニバーシティ オブ リーズ 改変されたプロテイナーゼインヒビター

Also Published As

Publication number Publication date
JPS6211736B2 (ja) 1987-03-14

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