JPS57162032A - Advance controlling system - Google Patents
Advance controlling systemInfo
- Publication number
- JPS57162032A JPS57162032A JP4748281A JP4748281A JPS57162032A JP S57162032 A JPS57162032 A JP S57162032A JP 4748281 A JP4748281 A JP 4748281A JP 4748281 A JP4748281 A JP 4748281A JP S57162032 A JPS57162032 A JP S57162032A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- address
- ibr1
- pointers
- indicating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
Abstract
PURPOSE:To execute an instruction at a high speed, by providing a pointer indicating from which position of an instruction buffer register the instruction is read out, and deriving an address of the instruction from value of the register indicating the advance instruction address, and an indicated position of the pointer. CONSTITUTION:A pipeline control computer is constituted by providing plural instruction buffer registers LBR1-IBR3, and each buffer IBR1-IBR3 is constituted of a prescribed byte. In accordance with said each byte, indicating pointers NSIP 0-3, 4-7 and 8-11 of 1 bit unit are provided. These pointers NSIP 0-11 are inputted to a selecting circuit SEC, and outputs of the buffers IBR1-3 are controlled. Subsequently, from a value of an advance instruction address of the buffers IBR1-3, and an indicated position of the pointers NSIP0-3-NSIP8-11, an address of an instruction is derived by the circuit SEC, generation of linkage information is quickened, and an execution cycle of a branch linkage instruction to a pipeline pL is shortened.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4748281A JPS57162032A (en) | 1981-03-31 | 1981-03-31 | Advance controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4748281A JPS57162032A (en) | 1981-03-31 | 1981-03-31 | Advance controlling system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57162032A true JPS57162032A (en) | 1982-10-05 |
JPH0315771B2 JPH0315771B2 (en) | 1991-03-01 |
Family
ID=12776343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4748281A Granted JPS57162032A (en) | 1981-03-31 | 1981-03-31 | Advance controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57162032A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5576446A (en) * | 1978-12-06 | 1980-06-09 | Toshiba Corp | Pre-fetch control system |
-
1981
- 1981-03-31 JP JP4748281A patent/JPS57162032A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5576446A (en) * | 1978-12-06 | 1980-06-09 | Toshiba Corp | Pre-fetch control system |
Also Published As
Publication number | Publication date |
---|---|
JPH0315771B2 (en) | 1991-03-01 |
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