JPH0315771B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction advance control method in electronic computers, etc., and in particular to branch linkage (BRANCH AND
This relates to advance control of LINK) instructions.

Generally, in data processing and calculation processing using electronic computers, etc., a proactive control method is used to speed up the execution speed of program instructions. A pipeline advance control method is used in which instructions are processed in parallel.

Normally, in this pipeline advance control method, the execution cycle of one instruction is divided into multiple cycles, and after several cycles of processing have progressed from the beginning of the multiple cycles, it is possible to process the next instruction in parallel. However, as an instruction that is used relatively frequently, there is a branch linking instruction (BAL) that returns to the next instruction before the branch after branch processing during the instruction to be executed and the processing after the branch.
There is. This branch linkage instruction (BRANCH
AND LINK), information from the current program status word PSW (updated next instruction address instruction length code (ILC), condition code (CC), program mask bit, etc.) is specified by the instruction as linkage information. Although storing in the general purpose register (GPR) is performed, the "updated next instruction address" that is part of the linkage information must indicate the next instruction address of the branch linkage instruction.
However, since advance control is being performed, the instruction address register (IAR) indicates several instructions ahead of the instruction address currently being executed, so the length of the preceding instruction must be corrected. For this reason, the execution cycle of the whole branch linking instruction becomes long.

An object of the present invention is to speed up the generation of the linkage information and shorten the execution cycle of branch linkage instructions.

In order to achieve the above object, the present invention includes a plurality of instruction prefetch buffers (IBR) divided into a plurality of areas, and a plurality of instruction prefetch buffers (IBR) provided for each of the plurality of areas. In addition to having a pointer (NSIP) that indicates the storage state of the instruction,
In the pipeline control computer, an instruction is stored in the instruction prefetch buffer in advance of the pipeline, and the pipeline control computer has an instruction address register (IAR) that holds an instruction address stored in the instruction prefetch buffer in advance of the pipeline. an instruction address register (IAR) that updates the value of the pointer (NSIP) when the instruction in the instruction is taken into the pipeline, and that indicates the preceding instruction address for reading the instruction; If the instruction fetched into the pipeline from the instruction prefetch buffer (IBR) is a branch-and-link instruction (BAL), the next instruction is fetched into the pipeline. Also, without updating the value of the pointer (NSIP), subtract the remaining number of bytes in the instruction prefetch buffer (IBR) obtained from the value of the pointer (NSIP) from the value of the preceding instruction address register (IAR). The feature is that the pointer (NSIP) is updated after calculating the return destination address.

The present invention will be explained in detail below with reference to Examples.

FIG. 1 is an explanatory diagram of command control which is the background of the present invention. In the figure, MEM refers to the memory device side,
The CPU indicates the processing device side, and the memory MEM stores a plurality of instruction groups 1 to 7, 1' to 3' and data (not shown). The processing unit CPU includes
Current program status word indicating current instruction execution status
Register that stores PSW, instruction buffer register IBR that holds instructions for pipeline advance control, pipeline PL that processes multiple instructions in parallel, arithmetic unit ALU, index register X, base register B, general-purpose register GPR
etc. The current program state word PSW contains
Instruction address register IAR indicating the address of the next instruction to be executed, instruction length code ICL of that instruction
(for example, 2-byte instructions, 4-byte instructions, etc.), a condition code CC based on the result of the instruction being executed, a program mask bit PMB, etc. In this configuration, for example, if the instruction being executed is (1), several steps of instructions are stored in the instruction buffer register IBR as advance control (in this example, instructions (1) to (4) are stored). ). and the current program state word
The PSW instruction address is the address indicated by arrow 10
a ₅ is indicated.

Here, the instruction is a branch linkage instruction according to the present invention.
BAL, and when the branch destination is after instruction (1)', the process of changing the instruction address IAR of the current program state word to address b ₁ shown by arrow 11, as described later, is executed again after branching. It is necessary to store the address _a2 of the next instruction 2 in a general-purpose register GPR or the like in order to return to the instruction (2) following the instruction (1) in the instruction.

FIG. 2 shows a configuration example (1) of this branch link instruction and a configuration example 2 of the next instruction address etc. stored in the general-purpose register. In the figure, branch linkage instruction 1
The operand part OP indicates the instruction function, the first operand part R1 specifies the general-purpose register number, the second operand part is the number specification X ₂ indicating the index register number, the number specification B ₂ indicating the base register number, and the address specification. D ₂ , it consists of a so-called RX instruction that performs operations on data in the memory device and register contents in the processing device, and sets the branch destination address to the contents of index register X, base register B, and a fixed value. D ₂ allows you to specify the first location in memory. That is, the instruction address of the branch destination is calculated by the arithmetic unit shown in FIG. 1, and the contents of the instruction address register of the current program state word PSW can be updated. On the other hand, the next instruction address (the next instruction address of the branch linked instruction before branching) is the instruction address of the current program state word (for example, a ₅ in Figure 1).
From the number of instructions in the instruction buffer register (3 of 2 to 4)
instruction) and is stored in the general-purpose register 2 along with the instruction length code ICL, condition code CC, and program mask bit MASK.
As shown in FIG. 3, ordinary processing instructions are executed in parallel. That is, in FIG. 3, each of the instructions 31 to 35 is processed in a plurality of processing cycles, as described above. D~
W indicates each state in each cycle,
D is a state where instructions are decoded;
R is a register read state for obtaining an operand address, A and B are states for generating an operand address for accessing a storage device from the contents of the read register and issuing an access request to the memory access unit, and B ₂ is the state in which the storage device is accessed using the obtained address, E ₁ and E ₂ are the states in which the operation is performed using the read operand data, and in the case of a store instruction, the state in which the operand data is stored in the storage device. , CK is a state in which data is checked, and W is a state in which the results of operations are written into various registers. A different instruction can enter the pipeline every two cycles in each cycle, and the next instruction is processed in parallel after two cycles of D state and R state are processed in the t direction in the figure, that is, in the time elapsed direction.

However, in the case of a branch-linked instruction under such advance control, the next instruction address of the currently processed instruction must be calculated and stored in a general-purpose register in advance, as described above. This control will be explained with reference to FIG. 4, which is an operation control diagram of a conventional branch linkage instruction. In FIG. 4, A1 indicates the processing state of the instruction that is executed first in advance control, and the branch linked instruction BAL is the D state of instruction A1, and the R
Indicates that the state is input to the pipeline PL in advance after two cycles of execution. Here, it is determined that the branch link instruction BAL is a branch link instruction in the decode state D and the register read state R, and as explained in FIG. The process is expanded into three flows and executed.

Flow (1) is a flow to find the branch destination instruction address and retrieve the branch destination instruction from the storage device, flow (2) is a dummy flow, and flow (3) is a flow to find linkage information and take it through the arithmetic unit. and writes to the general-purpose register (GPR) specified by the instruction. Conventionally, as a method for determining the "updated next instruction address," as shown in flow (3), a counter (HCTR) that indicates how many bytes precedes the instruction address register (IAR) that indicates the previous instruction address is used. It was calculated by subtracting the value and adding to it the instruction length of the branch linking instruction itself. That is, when a branch linkage instruction is executed,
For example, general purpose register GPRA,
Since the contents of GPRB are stored in the base register _BR and index register The branch destination instruction address is output by adding the contents of each register. The instruction address of this branch destination is sent to the effective address register EAR and the work address register, as well as to the memory access unit.
It sends the branch destination instruction address to the MAU, receives the instruction at the corresponding address from the memory device, and stores it in the instruction word register. Next, a dummy flow (2) is provided to calculate the next instruction address of the branch link instruction using the current program state word PSW. A/W is a bottom state (Wait State) for delaying the cycle.

The IAR in the next flow (3) is a register used to fetch instructions and indicates the start address of the last instruction group fetched, and indicates an address that precedes the address of the instruction currently being executed ( (See Figure 1). HCTR is a counter that holds the difference between the preceding instruction address and the currently executing instruction address, and IAR-HCTR is the currently executing instruction address.

HCTR is the instruction length (ILC) at the end of the instruction.
When calculating the next address with a branch link instruction, this subtracted HCTR is used, so the HCTR of the previous instruction is
Flow (3) was delayed until it was updated. Then, in flow (3), the instruction address register IAR of the instruction address of the current program state word PSW (that is, indicating the preceding instruction address), the constant register KR storing the instruction length BL of the branch linking instruction,
The displacement register DR, which stores the updated contents of the halfword counter HCTR, sequentially transfers its output to the execution address register EAR, work address register WAR, and second operand register 2R via the effective address generation adder EAG.

Control information for ILC, CC, and MASK of the current program status word PSW is also input to the second operand register 2R, and is stored in the general-purpose register GPR after being stored in the arithmetic unit ALU. The biggest problem here is the halfword counter
The problem is that it is not possible to proceed to flow (3) until the HCTR is updated, that is, the instruction length subtraction process of the previous instruction is completed. As a result, the start of the branch destination instruction is delayed, which is a factor that deteriorates the performance of branch linking instructions.

In the present invention, the processing speed and performance of branch-linked instructions are improved by generating instruction addresses by means completely different from conventional methods.

FIG. 5 is a diagram showing the structure of an instruction buffer register of the advance control system according to an embodiment of the present invention. In the figure, _IBR1 to _IBR3 are instruction buffer registers, and each buffer register has an 8-byte configuration. NSIP0-3, NSIP4-7, and NSIP8-11 correspond to each 2 bytes of each buffer register and indicate, for example, instruction pointers in units of 1 bit.

SEC is a selection circuit controlled by pointers NSIP0-11 and input to the pipeline PL. Then, a pointer (NSIP) is provided in 2-byte units for each of the multiple instruction buffer registers IBR ₁ to IBR ₃ , and this pointer is used to shift the contents of the instruction buffer register from instruction buffer register 3 to 2 to 1. Make sure to shift in sync. When the instruction in the instruction buffer register is taken into the pipeline, the pointer NSIP is configured to move to the beginning of the next instruction.

In other words, the selection circuit SEC inputs NSIP0-11 and transfers the instruction from the instruction buffer register IBR whose pointer is set to "1", that is, the instruction buffer register IBR located at the position corresponding to the pointer "1", to the pipeline PL. take in. And the said instruction is pipeline PL
When the command is fetched into the instruction, the control signal from the pipeline PL moves the pointer NSIP to the beginning of the next instruction.

The main feature of the present invention is that
This pointer is used instead of the HCTR to determine the difference between the address of the previous instruction and the address of the currently executing instruction, and this is subtracted from the previous instruction address (IAR). - An attempt was made to find the instruction address following the link instruction (BAL).

Specifically, IAR indicates the beginning of the last instruction buffer group. The value of this IAR is stored in instruction buffer registers IBR ₁ to IBR ₃ . By subtracting the number of bytes remaining after subtracting the number of bytes already taken into the pipeline from the number of bytes, the start address of the subsequent instruction can be found.
(The above operation will be described later.) During this operation, no subsequent instructions are input to the pipeline. Also, update of the pointer NSIP is stopped. That is, the instruction prefetch buffer (IBR)
If the instruction fetched into the pipeline is a branch-and-link instruction (BAL), the next instruction is not fetched into the instruction prefetch buffer register in the next cycle, and the previous instruction address (IAR) is The pointer is updated after calculating the return destination address by subtracting the remaining number of bytes in the instruction buffer registers IBR ₁ to _{IBR 3} obtained from the value of the pointer (NSIP).

When an instruction is fetched into the pipeline PL,
The instruction's opcode is decoded, and the decoding process determines whether the instruction is a BAL instruction or not.
Depending on the result, if the control signal from the pipeline PL to the pointer NSIP is stopped, the pointer will not be updated.

To give an example, if the number of bytes in each instruction buffer register is 8 bytes, and the pointer value is 2 at the time when the address correction value of the branch linking instruction described below is generated (B1 state), (at this time , the pointer is already pointing to the next instruction after the branch-linked instruction), and the number of bytes already taken into the pipeline is 4 bytes. Therefore, the remaining number of bytes in the instruction buffer registers IBR1-3 is 16-4=12 bytes. By subtracting this value from IAR, you can find the start address of the instruction following the branch-linked instruction. IAR-12 operations are performed using an arithmetic unit.

The advance control system for branch linkage instructions of the present invention will be explained with reference to FIG. FIG. 6 is an explanatory diagram of operation control using the advance control method of the present invention. In the figures, the same reference numerals as those used in FIG. 4 indicate the same parts. The difference from the conventional control (FIG. 4) is that the next instruction address of the branch linked instruction is determined.

Using the pointer (NSPI) explained in FIG. 5, the position information of the instruction at the time of execution (i.e., the pointer (NSPI) value) in the buffer register IBR is input to the address correction value circuit, and the number of bytes of the instruction to be subtracted ( or the number of words) in the first operand register.
1R, and instruction address register IAR, which stores the instruction address preceding the current program status word PSW, instruction word length ILC, condition code CC,
Store the mask bit MASK etc. to the second operand register 2R. In this instruction cycle, the address correction value can be generated at any time under the control of the pointer NSIP without having to wait until the end of instruction execution using the previous counter (HCTR), eliminating the need for a dummy flow as in the conventional system. Then, the arithmetic unit performs the IAR-address correction value operation, outputs the result to the result register (RR), and writes the value to the register indicated by the R1 section shown in FIG. 2A.

By performing the above operations, what conventionally required three flows can be done in one flow, and in this embodiment, the number of cycles can also be shortened by three cycles.

As explained above, according to the present invention, in the advance control method that processes multiple instructions simultaneously and in parallel, instructions that are part of branch linkage information are The address can be easily determined and the instruction execution speed can be increased. Therefore, the processing speed of the computer can be improved, which is extremely useful for information processing, etc., and the computer can be made larger, ie, the amount of information can be expanded.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of instruction control that is the background of the present invention, FIG. 2 is a block diagram of a branch-linked instruction as an example, and block diagram B of a general-purpose register, and FIG. 3 is an example of pipeline advance control. 4 is an operational control diagram of a conventional branch linkage instruction, FIG. 5 is a configuration diagram of an instruction buffer register in the advance control method of the present invention, and FIG. 6 is a diagram of operation control in the advance control method of the present invention. It is an explanatory diagram. IBR: Instruction buffer register, NSIP: Instruction pointer, SEL: Selection circuit, PL: Pipeline.

Claims (1)

[Claims] 1. A plurality of instruction prefetch buffers (IBR) divided into a plurality of areas, and a memory state of instructions for each of the plurality of areas provided corresponding to the instruction prefetch buffers (IBR). an instruction address register (IAR) that holds an instruction address stored in the instruction prefetch buffer in advance of the pipeline, and an instruction address stored in the instruction prefetch buffer in advance of the pipeline; A pipeline control computer having: updates the value of the pointer (NSIP) when an instruction in the area is taken into the pipeline;
The value of the pointer (NSIP) is updated in synchronization with the value of the instruction address register (IAR) indicating the preceding instruction address for reading the instruction, and the value of the pointer (NSIP) is updated in synchronization with the value of the instruction address register (IAR) indicating the preceding instruction address for reading the instruction, and the value of the pointer (NSIP) is updated in synchronization with the value of the instruction address register (IAR) indicating the preceding instruction address for reading the instruction. If the instruction is a branch-and-link instruction (BAL), the next instruction is not taken into the pipeline, the value of the pointer (NSIP) is not updated, and the previous instruction address register (IAR) is The feature is that the return destination address is calculated by subtracting the number of remaining bytes in the instruction prefetch buffer (IBR) obtained from the value of the pointer (NSIP) from the value of the pointer (NSIP), and then the pointer (NSIP) is updated. Advance control method.