JPS54100635A - Information processor - Google Patents

Information processor

Info

Publication number
JPS54100635A
JPS54100635A JP770178A JP770178A JPS54100635A JP S54100635 A JPS54100635 A JP S54100635A JP 770178 A JP770178 A JP 770178A JP 770178 A JP770178 A JP 770178A JP S54100635 A JPS54100635 A JP S54100635A
Authority
JP
Japan
Prior art keywords
instruction
branch
circuit
register
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP770178A
Other languages
Japanese (ja)
Inventor
Toshiyuki Furui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP770178A priority Critical patent/JPS54100635A/en
Publication of JPS54100635A publication Critical patent/JPS54100635A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To obtain an efficient leading control function with unneeded requests suppressed with respect to the leading process of a branch instruction, by enabling a memory unit to function to extract the instruction under specific conditions without sending out an instruction read request.
CONSTITUTION: The figure shows the look-ahead circuit. Instruction look-ahead control circuit 16 exercises a supervision over the idle state of register 11, fetches an instruction from a main memory unit not shown in the figure, and updates the contents of register 11. Now, a branch instruction is decoded by a processing part not shown in the figure and an computed branch-destination address is inputted to comparator circuit 17, so that the above-mentioned update operation will stop. On the basis of the contents of upper-limit and lower-limit address registers 13 and 14, comparator circuit 17 detects whether or not the branch-destination address is included in register 11. Judging from this result, circuit 16 determines whether or not the branch instruction should be read out from the main memory unit.
COPYRIGHT: (C)1979,JPO&Japio
JP770178A 1978-01-25 1978-01-25 Information processor Pending JPS54100635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP770178A JPS54100635A (en) 1978-01-25 1978-01-25 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP770178A JPS54100635A (en) 1978-01-25 1978-01-25 Information processor

Publications (1)

Publication Number Publication Date
JPS54100635A true JPS54100635A (en) 1979-08-08

Family

ID=11673054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP770178A Pending JPS54100635A (en) 1978-01-25 1978-01-25 Information processor

Country Status (1)

Country Link
JP (1) JPS54100635A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159154A (en) * 1982-03-18 1983-09-21 Yokogawa Hokushin Electric Corp Instruction loop catching mechanism for data processor
JPS59165144A (en) * 1983-03-07 1984-09-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Order extractor
JPS61256446A (en) * 1985-04-30 1986-11-14 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Instruction fetch buffer control
JPS626328A (en) * 1985-07-03 1987-01-13 Hitachi Ltd Information processor
JPH01239639A (en) * 1988-01-25 1989-09-25 Otto Muller Circuit apparatus and control for instruction buffer memory in data processor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159154A (en) * 1982-03-18 1983-09-21 Yokogawa Hokushin Electric Corp Instruction loop catching mechanism for data processor
JPS59165144A (en) * 1983-03-07 1984-09-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Order extractor
JPS61256446A (en) * 1985-04-30 1986-11-14 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Instruction fetch buffer control
JPS626328A (en) * 1985-07-03 1987-01-13 Hitachi Ltd Information processor
JPH01239639A (en) * 1988-01-25 1989-09-25 Otto Muller Circuit apparatus and control for instruction buffer memory in data processor

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