JPS57103560A - Stop controller of central processor - Google Patents

Stop controller of central processor

Info

Publication number
JPS57103560A
JPS57103560A JP55180874A JP18087480A JPS57103560A JP S57103560 A JPS57103560 A JP S57103560A JP 55180874 A JP55180874 A JP 55180874A JP 18087480 A JP18087480 A JP 18087480A JP S57103560 A JPS57103560 A JP S57103560A
Authority
JP
Japan
Prior art keywords
address
signal
program
level
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55180874A
Other languages
Japanese (ja)
Inventor
Genichi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55180874A priority Critical patent/JPS57103560A/en
Publication of JPS57103560A publication Critical patent/JPS57103560A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To facilitate the discontinuation for the execution of a program even in case the execution of the program is shifted from a specific processing part to another processing part and to avoid an nonexecution of the program, by designating a stop address within an address region. CONSTITUTION:An address signal 1 is supplied to both lower and upper limit comparators 9 and 10 according to the operation of a CPU to be compared with the contents of lower and upper limit registers 7 and 8 respectively. The comparator 10 delivers an H level when the address information of the signal 1 is set at a level higher than the address lower limit value; and the comparator 10 delivers an H level when the address information is set at a level lower than the address upper limit value. Then the execution of the program is shifted, an AND gate 13 or 14 is actuated by the output signal of an AND gate 11 plus a strobe signal 2. An interruption request signal 16 and its inverted signal 17 are delivered from an FF15.
JP55180874A 1980-12-19 1980-12-19 Stop controller of central processor Pending JPS57103560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55180874A JPS57103560A (en) 1980-12-19 1980-12-19 Stop controller of central processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55180874A JPS57103560A (en) 1980-12-19 1980-12-19 Stop controller of central processor

Publications (1)

Publication Number Publication Date
JPS57103560A true JPS57103560A (en) 1982-06-28

Family

ID=16090847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55180874A Pending JPS57103560A (en) 1980-12-19 1980-12-19 Stop controller of central processor

Country Status (1)

Country Link
JP (1) JPS57103560A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933542A (en) * 1982-08-18 1984-02-23 Nec Corp Display device
JPH03129439A (en) * 1989-07-05 1991-06-03 Nec Corp Debugging system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933542A (en) * 1982-08-18 1984-02-23 Nec Corp Display device
JPH03129439A (en) * 1989-07-05 1991-06-03 Nec Corp Debugging system

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