JPS57145357A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS57145357A
JPS57145357A JP56030863A JP3086381A JPS57145357A JP S57145357 A JPS57145357 A JP S57145357A JP 56030863 A JP56030863 A JP 56030863A JP 3086381 A JP3086381 A JP 3086381A JP S57145357 A JPS57145357 A JP S57145357A
Authority
JP
Japan
Prior art keywords
metal
bonding
inner wiring
film
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56030863A
Other languages
Japanese (ja)
Inventor
Tomoyuki Tsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56030863A priority Critical patent/JPS57145357A/en
Publication of JPS57145357A publication Critical patent/JPS57145357A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To avoid the damage of the circuit itself due to an overcurrent by providing a fuse metal in a part of an inner wiring metal when bonding is conducted at a projected part for wireless bonding of the inner wiring metal through the intermediary of an insulator film on a semiconductor substrate. CONSTITUTION:An SiO2 film 2 is connected to an Si substrate 1 whereat prescribed active and passive elements are formed and etching is applied thereto to make opening parts for connection which correspond to these elements. Next, while these opening parts being filled up, the inner wiring metal 3 such as Al having a metal projection 5 for wireless bonding is connected on the film 2. At this time, a part of the metal 3 is replaced with a Nichrome metal 7 by photoetching and vacuum evaporation or the like. According to this constitution, the metal 7 is fused if an excessive current runs at the time of bonding, whereby the damage of the circuit itself is avoided.
JP56030863A 1981-03-04 1981-03-04 Semiconductor integrated circuit Pending JPS57145357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56030863A JPS57145357A (en) 1981-03-04 1981-03-04 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56030863A JPS57145357A (en) 1981-03-04 1981-03-04 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57145357A true JPS57145357A (en) 1982-09-08

Family

ID=12315557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56030863A Pending JPS57145357A (en) 1981-03-04 1981-03-04 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57145357A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6190986B1 (en) 1999-01-04 2001-02-20 International Business Machines Corporation Method of producing sulithographic fuses using a phase shift mask

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147288A (en) * 1975-06-13 1976-12-17 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147288A (en) * 1975-06-13 1976-12-17 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6190986B1 (en) 1999-01-04 2001-02-20 International Business Machines Corporation Method of producing sulithographic fuses using a phase shift mask
US6278171B2 (en) 1999-01-04 2001-08-21 International Business Machines Corporation Sublithographic fuses using a phase shift mask

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