JPS57169261A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57169261A JPS57169261A JP5383881A JP5383881A JPS57169261A JP S57169261 A JPS57169261 A JP S57169261A JP 5383881 A JP5383881 A JP 5383881A JP 5383881 A JP5383881 A JP 5383881A JP S57169261 A JPS57169261 A JP S57169261A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- wiring
- opening
- shaped
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
PURPOSE:To prevent the disconnection of the wiring of the semiconductor integrated circuit device by filling the inside of an opening with a conductor and previously forming the upper surface of the opening in a flat surface the same as an insulating layer when the wiring and a functional region on a substrate are connected through the opening shaped to the insulating layer. CONSTITUTION:The insulating layers 3, 10 are formed onto the silicon substrate 1 to which the functional regions 8, 9 are shaped, and electrode windows 13 are formed according to a resist pattern 11. Alloying preventive layers between the silicon substrate and an aluminum layer, such as a tantalum film 14, a nitride tantalum film 15, etc. are shaped onto these whole surfaces, and an aluminum layer 17 is coated. The tantalum layers, etc. on the insulating layer 10 are removed together with a resist, and the aluminum layers 17 in the electrode windows are uniformly filled and flatterned through heating and melting. Accordingly, disconnection is not generated when wiring layers are formed onto the layers 17.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5383881A JPS57169261A (en) | 1981-04-10 | 1981-04-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5383881A JPS57169261A (en) | 1981-04-10 | 1981-04-10 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57169261A true JPS57169261A (en) | 1982-10-18 |
JPS6362103B2 JPS6362103B2 (en) | 1988-12-01 |
Family
ID=12953919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5383881A Granted JPS57169261A (en) | 1981-04-10 | 1981-04-10 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57169261A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02281736A (en) * | 1989-04-24 | 1990-11-19 | Sony Corp | Forming method of multilayer wiring |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS507430A (en) * | 1973-05-18 | 1975-01-25 | ||
JPS5187981A (en) * | 1975-01-31 | 1976-07-31 | Hitachi Ltd | HAISENSONOKEISEIHOHO |
JPS52106675A (en) * | 1976-03-05 | 1977-09-07 | Toshiba Corp | Manufacturing method of semiconductor device |
-
1981
- 1981-04-10 JP JP5383881A patent/JPS57169261A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS507430A (en) * | 1973-05-18 | 1975-01-25 | ||
JPS5187981A (en) * | 1975-01-31 | 1976-07-31 | Hitachi Ltd | HAISENSONOKEISEIHOHO |
JPS52106675A (en) * | 1976-03-05 | 1977-09-07 | Toshiba Corp | Manufacturing method of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02281736A (en) * | 1989-04-24 | 1990-11-19 | Sony Corp | Forming method of multilayer wiring |
Also Published As
Publication number | Publication date |
---|---|
JPS6362103B2 (en) | 1988-12-01 |
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