JPS5655062A - Formation of solder bump - Google Patents
Formation of solder bumpInfo
- Publication number
- JPS5655062A JPS5655062A JP13080679A JP13080679A JPS5655062A JP S5655062 A JPS5655062 A JP S5655062A JP 13080679 A JP13080679 A JP 13080679A JP 13080679 A JP13080679 A JP 13080679A JP S5655062 A JPS5655062 A JP S5655062A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- layer
- film
- solder bump
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To enable integration of solder bump by forming a substance not moistened with solder on a final passivation film before molting the solder film, melting the solder in this state, and forming a solder bump thereon. CONSTITUTION:A final passivation film 12 of electrode 11 and oxide film is coated on the upper surface of a substrate 10 made of semiconductor thin plate, a wiring layer 13 is formed thereon. The lower layer of the wiring layer is made of titanium layer 14 or the like which is not moistened with solder, and the upper layer is formed of a copper layer 15 of the like which is preferable adherence to the solder. A solder film 17 is formed at the window having the same size as the electrode 11 formed by photoetching. Subsequently, the photoresist film 16 is removed, is heated in the state that the copper layer 15 is removed, and a solder bump 18 is thus formed. Thus, when the solder is heated, the solder flowed to the titanium layer 14 is reduced, and the solder bump can be consequently integrated highly.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13080679A JPS5655062A (en) | 1979-10-12 | 1979-10-12 | Formation of solder bump |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13080679A JPS5655062A (en) | 1979-10-12 | 1979-10-12 | Formation of solder bump |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5655062A true JPS5655062A (en) | 1981-05-15 |
Family
ID=15043138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13080679A Pending JPS5655062A (en) | 1979-10-12 | 1979-10-12 | Formation of solder bump |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5655062A (en) |
-
1979
- 1979-10-12 JP JP13080679A patent/JPS5655062A/en active Pending
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