JPS5655063A - Formation of solder bump - Google Patents

Formation of solder bump

Info

Publication number
JPS5655063A
JPS5655063A JP13080979A JP13080979A JPS5655063A JP S5655063 A JPS5655063 A JP S5655063A JP 13080979 A JP13080979 A JP 13080979A JP 13080979 A JP13080979 A JP 13080979A JP S5655063 A JPS5655063 A JP S5655063A
Authority
JP
Japan
Prior art keywords
layer
solder
film
solder bump
forming region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13080979A
Other languages
Japanese (ja)
Inventor
Keiji Miyamoto
Toru Kawanobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13080979A priority Critical patent/JPS5655063A/en
Publication of JPS5655063A publication Critical patent/JPS5655063A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate the connection of adjacent solder bumps by forming an auxiliary layer which is not moistened with solder so as to surround a bump forming region. CONSTITUTION:A wiring layer 4 formed on the entire surface of the main surface of a substrate 1 is formed, for example, of a lower layer of titanium layer 5 having preferable adherence with aluminum, an upper layer of a copper layer 5 having good adherence with solder, and an auxiliary layer 11 made of Cr having low moistening property with the solder formed thereon. A ring-shaped portion 13 is formed on the portion of the solder bump forming region of the layer 11 by photoetching, and a solder film 8 is formed on the wiring layer 4. Then, the copper layer 6 and the titanium layer 5 are removed with the solder film 8 and the layer 11 retained, the film 8 is then heated and molten, and the semispherical solder bump 9 is formed by surface tension.
JP13080979A 1979-10-12 1979-10-12 Formation of solder bump Pending JPS5655063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13080979A JPS5655063A (en) 1979-10-12 1979-10-12 Formation of solder bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13080979A JPS5655063A (en) 1979-10-12 1979-10-12 Formation of solder bump

Publications (1)

Publication Number Publication Date
JPS5655063A true JPS5655063A (en) 1981-05-15

Family

ID=15043206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13080979A Pending JPS5655063A (en) 1979-10-12 1979-10-12 Formation of solder bump

Country Status (1)

Country Link
JP (1) JPS5655063A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
US6060769A (en) * 1996-09-20 2000-05-09 Micron Technology, Inc. Flip-chip on leads devices

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