JPS57145317A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57145317A
JPS57145317A JP56031046A JP3104681A JPS57145317A JP S57145317 A JPS57145317 A JP S57145317A JP 56031046 A JP56031046 A JP 56031046A JP 3104681 A JP3104681 A JP 3104681A JP S57145317 A JPS57145317 A JP S57145317A
Authority
JP
Japan
Prior art keywords
film
silicon layer
polycrystal
substrate
annealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56031046A
Other languages
Japanese (ja)
Inventor
Kenji Shibata
Tomoyasu Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56031046A priority Critical patent/JPS57145317A/en
Publication of JPS57145317A publication Critical patent/JPS57145317A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/2636Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form a semiconductor layer of excellent quality without giving chapping on the surface of a substrate by a method wherein a polycrystal or amorphous silicon layer is attached through an energy beam reflecting film to an insulated substrate and the silicon layer is annealed by the irradiation of enery beam. CONSTITUTION:SiO2 film 102 available for insulation film is formed on the surface of a polycrystal silicon substrate 101. Successively, Mo thin film 103 is vapor-deposited to the surface of the film 102 by a vapor deposition. Subsequently, a polycrystal silicon layer 104 of 5mum thickness is coated on the film 103. The silicon layer 104 is annealed by the irradiation of the electron beam from the upper position. According to such a processing, since the electron beam is reflected at the Mo film 103, an annealing efficiency can be raised, consequently the annealing can be estalished at a low power, the unevenness on the surface also be reduced remarkably and a problem of ring-fly is hardly caused.
JP56031046A 1981-03-04 1981-03-04 Manufacture of semiconductor device Pending JPS57145317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56031046A JPS57145317A (en) 1981-03-04 1981-03-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56031046A JPS57145317A (en) 1981-03-04 1981-03-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57145317A true JPS57145317A (en) 1982-09-08

Family

ID=12320531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56031046A Pending JPS57145317A (en) 1981-03-04 1981-03-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57145317A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124817A (en) * 1983-12-09 1985-07-03 Fujitsu Ltd Vapor-phase epitaxial growth method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5312607U (en) * 1976-07-15 1978-02-02
JPS5315527U (en) * 1976-07-22 1978-02-09

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5312607U (en) * 1976-07-15 1978-02-02
JPS5315527U (en) * 1976-07-22 1978-02-09

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124817A (en) * 1983-12-09 1985-07-03 Fujitsu Ltd Vapor-phase epitaxial growth method
JPH0554254B2 (en) * 1983-12-09 1993-08-12 Fujitsu Ltd

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