JPS57141737A - Channel controlling system - Google Patents

Channel controlling system

Info

Publication number
JPS57141737A
JPS57141737A JP2749181A JP2749181A JPS57141737A JP S57141737 A JPS57141737 A JP S57141737A JP 2749181 A JP2749181 A JP 2749181A JP 2749181 A JP2749181 A JP 2749181A JP S57141737 A JPS57141737 A JP S57141737A
Authority
JP
Japan
Prior art keywords
ccw
area
register
output
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2749181A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0122938B2 (enrdf_load_stackoverflow
Inventor
Masahito Hihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2749181A priority Critical patent/JPS57141737A/ja
Publication of JPS57141737A publication Critical patent/JPS57141737A/ja
Publication of JPH0122938B2 publication Critical patent/JPH0122938B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP2749181A 1981-02-26 1981-02-26 Channel controlling system Granted JPS57141737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2749181A JPS57141737A (en) 1981-02-26 1981-02-26 Channel controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2749181A JPS57141737A (en) 1981-02-26 1981-02-26 Channel controlling system

Publications (2)

Publication Number Publication Date
JPS57141737A true JPS57141737A (en) 1982-09-02
JPH0122938B2 JPH0122938B2 (enrdf_load_stackoverflow) 1989-04-28

Family

ID=12222597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2749181A Granted JPS57141737A (en) 1981-02-26 1981-02-26 Channel controlling system

Country Status (1)

Country Link
JP (1) JPS57141737A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131730A (en) * 1977-04-22 1978-11-16 Nec Corp Input/output control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131730A (en) * 1977-04-22 1978-11-16 Nec Corp Input/output control system

Also Published As

Publication number Publication date
JPH0122938B2 (enrdf_load_stackoverflow) 1989-04-28

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