JPS56118149A - Operating device - Google Patents

Operating device

Info

Publication number
JPS56118149A
JPS56118149A JP2136080A JP2136080A JPS56118149A JP S56118149 A JPS56118149 A JP S56118149A JP 2136080 A JP2136080 A JP 2136080A JP 2136080 A JP2136080 A JP 2136080A JP S56118149 A JPS56118149 A JP S56118149A
Authority
JP
Japan
Prior art keywords
bit
carry
output
mode
input data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2136080A
Other languages
Japanese (ja)
Inventor
Tadao Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2136080A priority Critical patent/JPS56118149A/en
Publication of JPS56118149A publication Critical patent/JPS56118149A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To make common the word operation circuits in two bit modes, different from the architecture of bits for one byte, by switching the carry output to the upper rank byte according to the effective bit of input data. CONSTITUTION:Carry output Ci-1 and two 9-bit input data Ai, Bi are input to an operation circuit 1 from the pre-stage. At 8-bit mode, the input data Ai, Bi are arranged right and fed to the operation circuit 1. The output control circuit 2 inputs the bit output BIi from the operation circuit, maximum carry CMi and specific bit carry CPi, and outputs the specific bit carry CPi being the carry of the 8th bit through selection as the carry output Ci, since the bit mode MB is in 8-bit mode. Further, if the result of operation is ''0'', the zero detection signal Zi is output. In case of 9-bit mode, the operation is made at normal mode.
JP2136080A 1980-02-21 1980-02-21 Operating device Pending JPS56118149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2136080A JPS56118149A (en) 1980-02-21 1980-02-21 Operating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2136080A JPS56118149A (en) 1980-02-21 1980-02-21 Operating device

Publications (1)

Publication Number Publication Date
JPS56118149A true JPS56118149A (en) 1981-09-17

Family

ID=12052922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2136080A Pending JPS56118149A (en) 1980-02-21 1980-02-21 Operating device

Country Status (1)

Country Link
JP (1) JPS56118149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05103740A (en) * 1991-10-15 1993-04-27 Akai Electric Co Ltd Floor brush for vacuum cleaner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05103740A (en) * 1991-10-15 1993-04-27 Akai Electric Co Ltd Floor brush for vacuum cleaner

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