JPS56124192A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS56124192A
JPS56124192A JP2408280A JP2408280A JPS56124192A JP S56124192 A JPS56124192 A JP S56124192A JP 2408280 A JP2408280 A JP 2408280A JP 2408280 A JP2408280 A JP 2408280A JP S56124192 A JPS56124192 A JP S56124192A
Authority
JP
Japan
Prior art keywords
input
read
output parts
data
data signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2408280A
Other languages
Japanese (ja)
Other versions
JPS6235192B2 (en
Inventor
Masaru Uesugi
Akira Makita
Nobuaki Ieda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2408280A priority Critical patent/JPS56124192A/en
Publication of JPS56124192A publication Critical patent/JPS56124192A/en
Publication of JPS6235192B2 publication Critical patent/JPS6235192B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make the read on high speed and extend the operation margin, by reducing the load capacity of the bit sense circuit array at the signal read time and by preventing every memory block from being influenced by unbalanced wiring capacities. CONSTITUTION:Data from memory cell array 21 read out through a pair of data signal input/output lines 23 of bit sense circuit array 22 is transferred to the first and second data signal input/output parts 26 and 27 of data signal transfer circuit 25. At this time, since MOSFETs 51 and 52 of circuit 25 are nonconductive by the control pulse, input/output parts 26 and 27 are cut off from the third and the fourth data signal input/output parts 28 and 29 of circuit 25, and the load capacity through a pair of input/output lines 301 is reduced at the data read time to perform high- speed read. Further, when FETs 51 and 52 are conductive, read data of input/ output parts 26 and 27 which are differentially amplified by MOSFETs 53-57 sufficiently are applied from input/output parts 28 and 29 to multiplexer 31 without the influence of unbalance of the wiring capacities, and thus, the operation margin is extended.
JP2408280A 1980-02-29 1980-02-29 Semiconductor memory Granted JPS56124192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2408280A JPS56124192A (en) 1980-02-29 1980-02-29 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2408280A JPS56124192A (en) 1980-02-29 1980-02-29 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS56124192A true JPS56124192A (en) 1981-09-29
JPS6235192B2 JPS6235192B2 (en) 1987-07-31

Family

ID=12128479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2408280A Granted JPS56124192A (en) 1980-02-29 1980-02-29 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS56124192A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03105790U (en) * 1990-02-19 1991-11-01

Also Published As

Publication number Publication date
JPS6235192B2 (en) 1987-07-31

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