KR870009393A - Dynamic Semiconductor Memory Device - Google Patents

Dynamic Semiconductor Memory Device Download PDF

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KR870009393A
KR870009393A KR870002908A KR870002908A KR870009393A KR 870009393 A KR870009393 A KR 870009393A KR 870002908 A KR870002908 A KR 870002908A KR 870002908 A KR870002908 A KR 870002908A KR 870009393 A KR870009393 A KR 870009393A
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semiconductor memory
memory device
dynamic semiconductor
transistor
circuit
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KR870002908A
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KR950002293B1 (en
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시게요시 와타나베
츠네아키 후세
코우지 사쿠이
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와타리 스기이치로
가부시키가이샤 도시바
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Priority claimed from JP61069933A external-priority patent/JPS62229595A/en
Priority claimed from JP62055357A external-priority patent/JP2659949B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

다이나믹형 반도체기억장치Dynamic Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예에 따른 다이나믹 RAM의 주요구성을 나타내는 회로도.1 is a circuit diagram showing the main configuration of a dynamic RAM according to the first embodiment of the present invention.

제2도는 본 발명의 제2실시예에 따른 다이나믹 RAM의 주요구성을 나타내는 회로도.2 is a circuit diagram showing the main configuration of a dynamic RAM according to a second embodiment of the present invention.

제3도는 본 발명의 제3실시예에 따른 다이나믹 RAM의 주요구성을 나타내는 회로도.3 is a circuit diagram showing a main configuration of a dynamic RAM according to a third embodiment of the present invention.

Claims (24)

다이나믹형 반도체기억장치에 있어서,In a dynamic semiconductor memory device, 기판상에 상호절연되어 교차되는 병렬워드선과 병렬비트선을 갖는 비트선쌍(BL,BL')가 포함되고,A pair of bit lines BL and BL 'having parallel word lines and parallel bit lines intersected and intersected on the substrate, 전계제어형으로 된 유니플라트랜지스터 및 캐패시터가 이용되어 구성되어져 상기 워드선과 비트선 사이의 교차부에 접속되는 메모리셀(10,20) 및,Memory cells 10 and 20, which are formed by using a uniplat transistor and a capacitor of an electric field control type and connected to an intersection between the word line and the bit line; 전계제어형의 유니폴라트랜지스터와 전류제어형의 바이폴라트랜지스터의 2종류를 이용하여 구성되면서 상기 비트선쌍(BL,BL')에 접속되어 상기 메모리셀 중에서 선택된 특정의 메모리셀에 저장된 데이터 신호를 독출하는 데이터독출모드에서 상기 비트선쌍(BL,BL')사이의 전위차를 검출하는 한편, 증폭하는 감지증폭기수단(14,16,24,50,52,54,56,200,202,210,212)으로 이루어지는 것을 특징으로 하는 다이나믹형 반도체기억장치.Data is constructed using two types of electric field controlled unipolar transistors and current controlled bipolar transistors, and connected to the bit line pairs BL and BL 'to read data signals stored in a specific memory cell selected from the memory cells. A dynamic semiconductor memory, characterized in that it consists of sensing amplifier means 14, 16, 24, 50, 52, 54, 56, 200, 202, 210 and 212 which detect the potential difference between the bit line pairs BL and BL 'in a read mode. Device. 제1항에 있어서, 감지증폭기수단은 바이폴라트랜지스터(T1,T2:T5,T6)에 의해 구성되는 구동부와 유니폴라트랜지스터에 의해 구성되는 부하부를 갖는 차동증폭회로(14,24)로 이루어진 것을 특징으로 하는 다이나믹형 반도체기억장치.The method of claim 1, wherein the sense amplifier means is characterized in that it comprises a differential amplifier circuit (14, 24) having a drive unit configured by bipolar transistors (T1, T2: T5, T6) and a load unit configured by a unipolar transistor. Dynamic semiconductor memory device. 제2항에 있어서, 유니폴라트랜지스터는 금속절연물반도체 전계효과형트랜지스터(Metal Insulator Semiconductor Field Effect Transistor)를 포함하고 있는 것을 특징으로 하는 다이나믹형 반도체기억장치.3. The dynamic semiconductor memory device according to claim 2, wherein the unipolar transistor includes a metal insulator semiconductor field effect transistor. 제3항에 있어서, 메모리셀과 더미셀은 금속절연물 반도체 전계효과형 트랜지스터와 캐패시터를 갖는 전류구동형 메모리셀(10)을 구성하게 되고, 특정의 메모리셀로부터의 데이터신호는 비파괴적으로 독출되는 것을 특징으로 하는 다이나믹형 반도체기억장치.4. The memory cell and the dummy cell constitute a current-driven memory cell 10 having a metal insulator semiconductor field effect transistor and a capacitor, wherein data signals from a particular memory cell are read non-destructively. A dynamic semiconductor memory device, characterized in that. 제3항에 있어서, 메모리셀과 더미셀은 금속절연물반도체전계효과형트랜지스터와 캐패시터를 갖는 전류구동형 메모리셀(20)을 구성하게 되는 것을 특징으로 하는 다이나믹형 반도체기억장치.4. The dynamic semiconductor memory device according to claim 3, wherein the memory cell and the dummy cell constitute a current driven memory cell having a metal insulator semiconductor field effect transistor and a capacitor. 제3항에 있어서, 감지증폭수단은 바이폴라트랜지스터(T5,T6)에 접속되어 데이터독출모드에서 특정의 메모리셀로부터 독출되는 데이터신호에 대해 바이폴라트랜지스터의 임피던스를 조정하는 임피던스변환수단(Q19,Q20)을 포함하여 이루어진 것을 특징으로 하는 다이나믹형 반도체기억장치.4. The impedance converting means (Q19, Q20) according to claim 3, wherein the sense amplifying means is connected to the bipolar transistors T5 and T6 to adjust the impedance of the bipolar transistor with respect to the data signal read out from a specific memory cell in the data reading mode. Dynamic semiconductor memory device, characterized in that consisting of. 제6항에 있어서, 임피던스변환수단(Q19,Q20)은 바이폴라트랜지스터(T5,T6)의 베이스전극에 직렬로 접속되어 그 바이폴라트랜지스터(T5,T6)의 베이스전류를 조절하는 고임피던스소자인 것을 특징으로 하는 다이나믹형 반도체기억장치.7. The impedance conversion means (Q19, Q20) is a high impedance device for controlling the base current of the bipolar transistors (T5, T6) connected in series with the base electrodes of the bipolar transistors (T5, T6). Dynamic semiconductor memory device. 제1항에 있어서, 감지증폭기수단은 베이스전극과 컬렉터전극을 갖추고 구동부로서의 기능을 하게 되는 바이폴라트랜지스터 및 유니폴라트랜지스터에 의해 구성되는 BIMOS형 차동증폭회로(56,102)와, 비트선과 상기 BIMOS형 차동증폭회로를 구성하는 바이폴라트랜지스터의 베이스전극에 접속되어 데이터독출모드에서 특정의 메모리셀로부터 독출된 데이터신호에 대해 바이폴라트랜지스터의 임피던스를 조정하는 임피던스변환회로수단(52,100)으로 이루어진 것을 특징으로 하는 다이나믹형 반도체기억장치.2. The sensing amplifier means according to claim 1, wherein the sensing amplifier means includes a BIMOS differential amplifier circuit 56 and 102 constituted by a bipolar transistor and a unipolar transistor having a base electrode and a collector electrode to function as a driving unit, and bit lines and the BIMOS type differential amplifier. A dynamic semiconductor device comprising impedance conversion circuit means (52, 100) connected to a base electrode of a bipolar transistor constituting a circuit to adjust the impedance of a bipolar transistor with respect to a data signal read from a specific memory cell in a data read mode. Memory. 제8항에 있어서, 임피던스 변환회로수단은 유니폴라트랜지스터에 의해 구성되는 MOS형 차동증폭회로(52,100)로 구성되는 것을 특징으로 하는 다이나믹형 반도체기억장치.9. The dynamic semiconductor memory device according to claim 8, wherein the impedance conversion circuit means comprises a MOS differential amplifier circuit (52, 100) constituted by a unipolar transistor. 다이나믹형 반도체기억장치에 있어서,In a dynamic semiconductor memory device, 기판상에 설치된 복수쌍의 비트선(BL,BL')과,A plurality of pairs of bit lines BL and BL 'provided on the substrate, 이 비트선(BL,BL')과 절연되어 교차되는 워드선(WL),A word line WL insulated from and intersecting the bit lines BL and BL ', 전계제어형의 유니폴라트랜지스터와 캐패시터를 갖으면서 비트선(BL,L')과 워드선(WL) 사이의 교차점에 설치되는 각각의 메모리셀(20a,20b),Memory cells 20a and 20b each having an electric field control type unipolar transistor and a capacitor and installed at an intersection point between the bit lines BL and L 'and the word line WL, 복수쌍의 비트선(BL,BL')에 접속되고, 특정의 비트선쌍(BL,BL')에 설치되어 있는 곳의 선택된 메모리셀(20a)에 저장된 데이터신호를 독출하는 독출모드에서 상기 비트선쌍(BL,BL') 사이의 전유차를 검출하여 독출데이터신호를 생성하게 되는 특정의 비트선쌍에 접속되면서 상호 병렬로 접속되어 상기 전위차를 증폭하는 최소한 하나이상의 MOS형 플립플롭회로(50,54)와, 비트선쌍에 접속되면서 MOS형 플립플롭회로에 병렬로 접속되는 MOS형 차동증폭회로(52,200,210) 및 , 상기 MOS형 차동증폭회로수단과 상기 MOS형 플립플롭회로에 접속되어 바이폴라트랜지스터에 의해 구성되는 구동부와 부하부를 갖는 BIMOS형 차동증폭회로(56,202,212) 등으로 구성되는 감지증폭기수단 및,The bit is read in a read mode that is connected to a plurality of pairs of bit lines BL and BL 'and reads out a data signal stored in the selected memory cell 20a where it is provided in a specific bit line pair BL and BL'. At least one MOS flip-flop circuit (50, 54) which is connected in parallel to each other and is connected to a specific bit line pair which detects an electric difference between the line pairs (BL, BL ') to generate a read data signal and amplifies the potential difference. ), MOS type differential amplification circuits 52, 200, and 210 connected in parallel to a MOS type flip flop circuit while being connected to a pair of bit lines, and a bipolar transistor connected to the MOS type differential amplifying circuit means and the MOS type flip flop circuit. A sense amplifier means comprising a BIMOS type differential amplifier circuit 56, 202, 212 having a driving part and a load part; 상기 감지증폭기수단에 접속되어 상기 BIMOS형 차동증폭회로의 출력신호를 받는 1쌍의 신호출력선(OL1,OL2)을 구비하여 이루어진 것을 특징으로 하는 다이나믹형 반도체기억장치.And a pair of signal output lines (OL1, OL2) connected to said sense amplifier means for receiving an output signal of said BIMOS type differential amplifier circuit. 제10항에 있어서, 바이폴라트랜지스터는 MOS형 차동증폭회로(52,200,210)에 접속되는 베이스전극과 플립플롭회로(54)와 1쌍의 신호출력선(OL1,OL2)에 접속되는 컬렌터전극을 갖는 제1 및 제2의 바이폴라트랜지스터(T10,T12:T14,T16,T18,T20)이고, 상기 MOS형 차동증폭회로는 BIMOS형 차동증폭회로의 제1 및 제2의 바이폴라트랜지스터(T10,T12:T14,T16,T18,T20)의 입력임피던스 변환장치로서의 기능을 하게 되어 있는 것을 특징으로 하는 다이나믹형 반도체기억장치.11. The bipolar transistor according to claim 10, wherein the bipolar transistor has a base electrode connected to the MOS differential amplifier circuits (52, 200, 210), a flip-flop circuit (54), and a collector electrode connected to a pair of signal output lines (OL1, OL2). The first and second bipolar transistors (T10, T12: T14, T16, T18, T20), and the MOS type differential amplifier circuits include the first and second bipolar transistors (T10, T12: T14, A dynamic semiconductor memory device characterized in that it functions as an input impedance converter of T16, T18, and T20. 제11항에 있어서, 제1 및 제2의 바이폴라트랜지스터(T10,T12:T14,T16,T18,T20)의 컬렉터전극과 CMOS형 플립플롭회로(54)의 사이에는 유니폴라트랜지스터에 의해 구성되어 직렬로 설치되는 전송회로(Q54,Q56:Q54',Q56')가 추가로 구비된 것을 특징으로 하는 다이나믹형 반도체기억장치.12. The device of claim 11, wherein the collector electrodes of the first and second bipolar transistors (T10, T12: T14, T16, T18, T20) and the CMOS flip-flop circuit 54 are configured by unipolar transistors in series. And a transmission circuit (Q54, Q56: Q54 ', Q56') which is installed as an additional type. 제12항에 있어서, BIMOS형 차동증폭회로(202)는 복수의 비트선쌍에 대해 각각 설치되는 것을 특징으로 하는 다이나믹형 반도체기억장치.13. The dynamic semiconductor memory device according to claim 12, wherein the BIMOS type differential amplification circuit (202) is provided for a plurality of bit line pairs, respectively. 제12항에 있어서, BIMOS형 차동증폭회로(56)는 특정의 비트선쌍과 그 비트선쌍에 인접되는 비트선쌍에 공통으로 설치되는 것을 특징으로 하는 다이나믹형 반도체기억장치.13. The dynamic semiconductor memory device according to claim 12, wherein the BIMOS differential amplifier circuit (56) is provided in common in a specific bit line pair and a bit line pair adjacent to the bit line pair. 제12항에 있어서, BIMOS형 차동증폭회로(56,202)의 출력이 CMOS형 플립플롭회로에 입력되는 것을 특징으로 하는 다이나믹형 반도체기억장치.13. A dynamic semiconductor memory device according to claim 12, wherein the output of the BIMOS differential amplifier circuit (56,202) is input to a CMOS flip-flop circuit. 제15항에 있어서, 플립플롭회로는 BIMOS형 차동증폭회로(56,202)의 출력이 최초로 입력되는 제2의 CMOS플립플롭회로(54)와 입력된 신호를 더욱 증폭해 주는 제1의 CMOS플립플롭회로(56)를 갖추고 있는 것을 특징으로 하는 다이나믹형 반도체기억장치.16. The flip-flop circuit of claim 15, wherein the flip-flop circuit includes a second CMOS flip-flop circuit (54) to which the outputs of the BIMOS type differential amplification circuits (56, 202) are first input, and a first CMOS flip-flop circuit that further amplifies the input signal. 56. A dynamic semiconductor memory device, comprising: 56; 제10항에 있어서, MOS차동증폭회로(52,200,210)는 그 1쌍의 출력중에서 한쪽출력이 게이트가 공통접속되어 부하부를 이루는 유니폴라트랜지스터에 귀환되는 것을 특징으로 하는 다이나믹형 반도체기억장치.11. The dynamic semiconductor memory device according to claim 10, wherein the MOS differential amplifier circuits (52, 200, 210) return one of the pair of outputs to a unipolar transistor whose gate is commonly connected to form a load portion. 제10항에 있어서, MOS차동증폭회로(52,200,210)는 최소한 하나이상의 활성화용 유니폴라트랜지스터를 구비하게 되고, 이 유니폴라트랜지스터는 선형영역에서 동작하게 되는 것을 특징으로 하는 다이나믹형 반도체기억장치.11. A dynamic semiconductor memory device according to claim 10, wherein the MOS differential amplifier circuits (52, 200, 210) comprise at least one unipolar transistor for activation, the unipolar transistors operating in a linear region. 제10항에 있어서, MOS형 차동증폭회로는 최소한 하나이상의 활성화용 유니폴라트랜지스터를 구비하게 되고, 이 유니폴라트랜지스터는 포화영역에서 동작하게 되는 것을 특징으로 하는 다이나믹형 반도체기억장치.11. The dynamic semiconductor memory device according to claim 10, wherein the MOS differential amplifier circuit includes at least one unipolar transistor for activation, and the unipolar transistor is operated in a saturation region. 제10항에 있어서, MOS형 차동증폭회로는 게이트가 공통접접되어 기준전위가 공급되는 부하부의 유리폴라트랜지스터와 활성화용 유니폴라트랜지스터를 갖추고, 이 활성화용 유니폴라트랜지스터는 선형영역에서 동작되도록 구성된 것을 특징으로 하는 다이나믹형 반도체기억장치.11. The MOS type differential amplifying circuit according to claim 10, wherein the MOS type differential amplifying circuit has a glass polar transistor and an activating unipolar transistor in a load portion in which a gate is commonly contacted to supply a reference potential, and the unipolar transistor for activation is configured to operate in a linear region. A dynamic semiconductor memory device. 제10항에 있어서, BIMOS형 차동증폭회로(56,202)는 최소한 하나이상의 활성화용 유니폴라트랜지스터를 구비하게 되고, 로우어드레스스트로브신호에 의해 활성화되게 되어 있는 것을 특징으로 하는 다이나믹형 반도체기억장치.11. A dynamic semiconductor memory device according to claim 10, wherein the BIMOS type differential amplification circuit (56,202) includes at least one unipolar transistor for activation and is activated by a low address strobe signal. 제21항에 있어서, 활성화는 예비활성화인 것을 특징으로 하는 다이나믹형 반도체기억장치.23. The dynamic semiconductor memory device according to claim 21, wherein the activation is preliminary activation. 제10항에 있어서, MOS차동증폭회로는 최소한 하나이상의 활성화용 유니폴라트랜지스터를 갖추고서 로우어드레스 스트로브신호에 의해 활성화되게 되어 있는 것을 특징으로 하는 다이나믹형 반도체기억장치.11. The dynamic semiconductor memory device according to claim 10, wherein the MOS differential amplifier circuit has at least one unipolar transistor for activation and is activated by a low address strobe signal. 제23항에 있어서, 활성화는 예비활성화인 것을 특징으로 하는 다이나믹형 반도체기억장치.24. The dynamic semiconductor memory device according to claim 23, wherein the activation is preliminary activation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870002908A 1986-03-28 1987-03-28 Dynamic semiconductor memory device KR950002293B1 (en)

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JP61-69933 1986-03-28
JP61069933A JPS62229595A (en) 1986-03-28 1986-03-28 Dynamic semiconductor memory device
JP69933 1986-03-28
JP62-55357 1987-03-12
JP62055357A JP2659949B2 (en) 1987-03-12 1987-03-12 Dynamic semiconductor memory device

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US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
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