JPS62229595A - Dynamic semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain high speed operation and cost reduction per bit by using an amplifier, which employs a bipolar transistor (TR) as a driver, as a sense amplifier for a dynamic RAM. CONSTITUTION:In selecting a word line 61 and a dummy word line 62 at read, the data of a memory cell 1 and a dummy cell 2 are sent to bit lines 51, 52. At the time of a column selection signal is given, MOS TRs Q6, Q7 are turned on, the data of the bit lines 51, 52 are sent to I/O lines 71, 72 and its signal difference is read by a sense amplifier 3. The amplifier 3 uses bipolar TRs T1, T2 for the driver and a BIMOS structure differential amplifier using MOS TRs Q1, Q2 is used, then the high speed operation and high circuit integration the same degree as the static RAM are attained. Thus, the high speed performance and cost-reduction are attained.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a dynamic semiconductor memory device.

(Technical background of the invention and its problems) MOS type semiconductor memory devices are becoming increasingly finer and faster.

Currently, 41c or 16-inch static RAM (s RAM) is often used in fields where high speed is required, such as cache memory in large computers. However, the gate length of the MOS transistor is 0.5 μm.
When miniaturization progresses to a certain level, the external power supply must be lowered to ensure element reliability, and it will no longer be possible to increase speed through miniaturization as in the past. Therefore, s
In RAM, speeding up has been achieved by introducing bipolar transistors which have a larger current driving capability than MOS transistors.

FIG. 3 shows an example of such an sRAM. The memory cell 21 includes a bistable circuit consisting of a MOS transistor Q41, Q42 and load resistors R1, R2, and a MOS transistor Q43, . It consists of Q44. When word line 23 is selected, cell data is transferred to bit line 24.25, and when MOS transistors Q47 and Qta are turned on by the column selection signal, the data on bit line 24.25 is transferred to I10 line 26.2.
Transferred to 7. The data on the I10 line 26.27 uses the bipolar transistor T21°T22 as the driver,
The signal is amplified by a sense amplifier 22 configured by connecting load resistors R3 and R4. Qe9 is a sense amplifier activation MOS transistor.

This structure is a combination of a bipolar transistor and a CMOS element, and is called B I CMOS. With this), Q configuration, since a bipolar transistor is used in the sense amplifier 22, data on the I10 lines 26 and 27, which have a large load capacity, can be amplified at high speed. Therefore, the speed of sRAM can be increased.

FIG. 4 shows a comparison of the delay time characteristics of 0MO3 and BICMOS. In both cases, using the 1.2 μm rule, 15
The delay time characteristics were measured using a staged NAND oscillator. As is clear from this figure, in BICMOS, which is a combination of bipolar transistor and CMOS,
Compared to CMOS, the larger the load capacity, the greater the advantage of speeding up.

By the way, as shown in Figure 3, sRAM has a memory cell composed of hexagonal elements, so compared to dynamic RAM (dRAM) where memory cells are usually composed of four or less elements, it is possible to achieve higher integration when using the same gate length. cannot be converted into For example, in order to achieve the same degree of integration, the gate length of sRAM must be 60 to 70% that of dRAM.

In other words, sRAM is suitable for speeding up, but dRA
The essential drawback is that it cannot be as highly integrated as M.
64k cache memory.

When further integrating IM into H.256, it is difficult to achieve low cost per bit and high speed using sRAM.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points.
The object of the present invention is to provide a dRAM that enables high integration while maintaining high speed and reduces the cost per bit.

[Summary of the invention]

The present invention provides a dR memory cell configured with one or more field effect transistors and one capacitor.
AM is characterized by using an amplifier using a bipolar transistor as a driver as a sense amplifier.

〔Effect of the invention〕

According to the present invention, by using a bipolar transistor for the driver of the sense amplifier, high-speed operation comparable to that of sRAM is possible, and the cost per bit is low.
AM can be obtained.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 is an equivalent circuit showing the main part of a dRAM according to an embodiment. As the memory cell 1, a current-driven memory cell composed of three MOS transistors Qa r Qe + Q+ o and one capacitor C1 is used. The reason why a current-driven memory cell is used is that it is preferable to use a bipolar transistor as a driver of a sense amplifier, which will be explained later. Dummy cell 2 similarly includes three MOS transistors Q11. Q121Q13
and one capacitor C2. The figure shows a state where one memory cell 1 is connected to the bit line 51 and one dummy cell 2 is connected to the bit line 52, but in reality, many memory cells and one dummy cell are connected to each bit line. In this state, an array is formed on a semiconductor substrate. 61.
Reference numerals 62 denote a word line and a dummy word line, respectively, by which switching MOS transistors Q a + 011 of memory cell 1 and dummy cell 2 are selectively driven. Q4. Q5 is a MOS transistor serving as a load for memory cells and dummy cells. Q6 and Q7 are transfer gate MOS transistors connecting the bit lines 51, 52 and I10 lines 7□, 72, which are selectively driven by a column selection signal. I10 line 7. ．． The sense amplifier 3 connected to 72 is configured by a BIMOS differential amplifier using bipolar transistors "1 + T2 as a driver and MoS transistors QL and Q2 as loads. Q3 is for activation. In this embodiment, the output amplifier 4 connected to the output lines 81 and 82 of the sense amplifier 3 uses a bipolar transistor T3゜I5 as a driver and MOS transistors Q14 and QI5 as a load. B
A differential amplifier with an IMOS structure is used.

With this configuration, when word line 61 and dummy word line 62 are selected during reading, the data of memory cell 1 and dummy cell 2 are transmitted to bit lines 51 and 52, respectively. When a column selection signal is input, MOS+- transistors Q6 and Q7 are turned on, and bit lines 5□, 52
are transmitted to the I10 lines 71 and 72, respectively, and the sense amplifier 3 reads out the signal difference between them.

According to this embodiment, since a BIMOS differential amplifier is used as the sense amplifier, high-speed sensing operation is possible. In particular, when the load capacity of the sense amplifier increases due to high integration, the effect of speeding up is large as described above, and a dRAM capable of operating at a high speed comparable to that of an sRAM can be obtained. Further, this embodiment uses a current-driven memory cell structure, which is a non-destructive read type. Therefore, there is no need to wait until bit line data is determined to select a column, unlike when using a one-transistor/one-capacitor charge readout type memory cell, which is also advantageous for high-speed operation.

Furthermore, even if a current-driven memory cell is used, the number of constituent elements is smaller than that of an sRAM memory cell. Therefore, according to this embodiment, it is possible to obtain a dRAM that can operate at a high speed comparable to that of an sRAM and has a low cost per bit.

Furthermore, since bipolar elements generally have better temperature characteristics than MOS elements and are less affected by power supply voltage fluctuations, this embodiment provides a highly reliable memory element. Therefore, the test process for the memory device is also shortened and costs are reduced.

Furthermore, bipolar devices are generally more resistant to variations in process parameters than MOS devices, so the introduction of bipolar transistors makes manufacturing easier.
Efforts are being made to reduce costs through mass production.

Furthermore, the dependence of the dynamic characteristics of a bipolar element on load capacitance is much smaller than that of a MOS element alone. Therefore, it is not necessary to accurately estimate the load capacity as in the conventional case when designing a memory, thereby shortening the design period.

FIG. 2 is an equivalent circuit showing the main structure of a dRAM according to another embodiment. In this embodiment, one MOS transistor Q is used as the memory cell 11 and the dummy cell 12, respectively.
27. A charge reading type using Q28 and one capacitor C11, CI2 is used. 15. ．． 152 are bit lines, 16, . 162 is a word line. bit line 15
The sense amplifier 13 connected to 1.152 uses a bipolar transistor T11゜T1□ as a driver,
MOS transistor Q21. as a load. This is a differential amplifier using Q22.

Q23. Q24 is a sense amplifier activation MOS transistor. Since a charge read type is used for the memory cell 11 and the dummy cell 12, and a bipolar transistor is used for the driver of the sense amplifier 13, it is necessary to prevent the "H" level from dropping during read. MO serving as a high resistance element at the base of the driver transistor T11゜TI2 of the sense amplifier 13
An S transistor Q25.026 is inserted. Bit line 15. ．． 152, transfer gate MOS transistors Q2 each driven by a column selection signal.
9. I10 lines 17, . 172 is connected. As the output amplifier 14 provided to the I10 lines 171 and 172, bipolar transistors T13 and T14 are used as drivers, and a MOS transistor Q is used as the load.
3□.

A differential amplifier using Q32 is used.

It is clear that this embodiment also provides the same effects as the previous embodiment.

The present invention is not limited to the above embodiments, and can be implemented with various modifications without departing from the spirit thereof.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram showing the main part configuration of a dRAM according to one embodiment of the present invention, Fig. 2 is an equivalent circuit diagram showing the main part composition of another embodiment, and Fig. 3 is an example of the structure of a conventional sRAM. FIG. 4 is a diagram showing a comparison of the delay time characteristics of a CMOS structure and a BICMOS structure. 1...Memory cell, 2...Dummy cell, 3...Sense amplifier, 4...Output amplifier, 5□, 52...Bit line, 6. ．． 62...word line, 7. ．． 72...
T10 line, 81, 82...output line, "r, + T2
, T3 +T4...Bipolar transistor (driver), 11...Memory cell, 12...Dummy cell,
13...Sense amplifier, 14...Output amplifier, 15
1,152...Bit line, 161.162...Word line, 171°172...T10 line, Tl 1 +
TI2, T13. T, 4... Bipolar transistor (driver). Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4

Claims (3)

[Claims] (1) In a dynamic semiconductor memory device in which dynamic memory cells constituted by one or more field effect transistors and one capacitor are arranged and formed on a semiconductor substrate, a sense amplifier reads output data of the memory cells. A dynamic semiconductor memory device characterized in that it uses an amplifier using a bipolar transistor as a driver. (2) The dynamic semiconductor memory device according to claim 1, wherein the sense amplifier is a differential amplifier whose driver is a pair of bipolar transistors into which the output of a selected memory cell and the output of a dummy cell are input. . (3) The dynamic semiconductor memory device according to claim 1, wherein an amplifier having a bipolar transistor as a driver is used as an amplifier provided on an output line to which an output terminal of the sense amplifier is connected.