JPS5948892A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device of plural board semiconductors which has a simple constitution, by controlling independently a storage memory cell and a reading memory cell after connecting these cells to different word lines and bit lines, respectively. CONSTITUTION:Storage cells S1, S2- of a matrix array including transistor pairs 201, 202, etc. connected with cross to each other are connected to the 1st word lines 211, 215- and the 1st bit lines 219 and 220 as well as 223 and 224-, etc. While reading memory cells M1, M2- comprising active switches of differential transistor pairs 205, 206, etc. having their emitters connected in common are connected to the 2nd word lines 212, 216- different from the cells S1, S2- as well as to bit lines 221 and 222, 225 and 226-. The cells M1, M2- and cells S1, S2- are controlled independently of each other. Then the storage contents of cells S1, S2- are converted into signal levels on the basis of the lines 212, 216- and then read out of cells M1, M2-. In such a way, it is possible to obtain a semiconductor storage device of plural boards, e.g., two boards, etc. which has a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application The present invention relates to a semiconductor memory device, and is intended to realize a multi-port memory device with a simple circuit configuration.

Conventional Structures and Problems Today's digital signal processing requires complex functions, and storage devices are also required to have the ability to read multiple data at the same time, and the ability to write and read data at the same time. A multi-port storage device is designed to handle such requests, and has multiple addresses. One finite address is an address that can be written to and read from, and the remaining addresses P, J', and g'j This is a private address.

In this way, multi-port semiconductor memory devices are commonly used in devices that can use transfer gates, such as MO3 type semiconductors, but in bipolar type semiconductors used for high-speed signal processing, transfer gate Conventionally, a one-port device with one address signal was common.

FIG. 1 shows a part of a memory cell of a conventional semiconductor memory device. 101 and 102 are multi-emitter transistor pairs whose bases and collectors are cross-connected;
3,104 is a load resistance. 1o1゜102.103
, 104 is a 1-bit memory cell. C2, C3, and C4 are memory cells having the same configuration as C1, and such memory cells are arranged for the total memory capacity to constitute the entire memory device. 1o5 and 107 are word lines; 106 and 108 are lines to which one emitter of the multi-emitter transistor of each memory cell is commonly connected;
Connected to a constant current source (not shown). Word line 105,1
07 are each connected to an address decoder, and have a high potential when selected and a low potential when not selected. 109,11
0, 111, 112 are bit lines and constant current sources 113~
116, and the read data and write data of the selected word are input and output to this line.

A read operation of such a memory device is performed by setting the word line of the word to be read to a high potential using the address decoder output. Furthermore, since the emitters of the multi-emitter transistor pairs in each memory cell are commonly connected to the data line, this data line has the highest potential among the base potentials of the multi-emitter transistor pairs in each memory cell. Something is output. That is, the data content of the memory cell whose word line has a high potential is output.

In addition, the seeding operation adds write data to the data line, and in the memory cell where the word line is at a high potential, the current of the constant current circuit connected to the data line is caused to flow from which transistor of the multi-emitter transistor pair. By Sky,
I have one piece of writing.

As described above, in the conventional memory device, there is only one address, and therefore, read data can only be read from one memory cell. Also, writing and reading cannot be performed at the same time.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to realize a multi-port semiconductor memory device with a simple circuit configuration.

Structure of the Invention The present invention includes a memory cell having a memory function connected to a first word line and a first bit line, and a memory cell having a memory function connected to a first word line and a first bit line; and a readout cell connected to the first. This semiconductor memory device is characterized in that second word lines are controlled separately.

DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows an embodiment of the present invention, in which a two-port case is shown.

A memory cell S1 composed of multi-emitter transistors 201, 202 and resistors 203, 204 has the same structure as the memory cell explained in the conventional example of FIG.
, 84 also have the same configuration as this 81. 211°21
Reference numeral 5 denotes a first word line which has a high potential when selected and a low potential when not selected according to a signal from the first address decoder.

This first address decoder is controlled by a first address signal.

213 and 217 are lines to which one emitter of the multi-emitter transistor of each memory cell is commonly connected, and is connected to a constant current source. 219, 220 and 223゜2
24 is the first bit line, 227, 228 and 231°2
32 is a constant current source, and the first word line, first bit line, and constant current source are connected in the same way as in the conventional example shown in FIG. In other words, when reading, the data stored in the memory cell of the word selected by the first address is output to the first bit line, and when writing, the data input to the first bit line is selected by the first address. written to the word's storage cell.

In the operation of such a conventional memory device, a circuit for reading stored data using a second address signal will be described below.

In FIG. 2, a differential switch is configured by a differential transistor pair 205, 206 whose emitters are commonly connected and a resistor 207, 208.
The base of 5,206 is connected to the collector of multi-emitter transistor pair 202,201 of storage cell S1. The data stored in the storage cell S1 is input to the switching differential switch. The output of the differential switch is a transistor 209 whose emitter is tangent to the second bit line 221,222.
, 210.

Transistors 205, 206 and resistors 207, 208
The readout cell R1 is composed of a differential switch and a transistor 2o9°210, and R2°R
3, R4 has the same configuration as this R1.

A second word line 212 is driven by a second address control signal via a second address decoder, and has a high potential when selected and a low potential when not selected.

214 and 218 are lines to which the emitters of the differential transistor pair are commonly connected, and are connected to a constant current source.

221, 222, 225, 226 are second bit lines, and the read data of the word selected by the second address decoder is output to these lines. 229°230
and 233, 234 are constant current sources.

Here, in the read cell R1, since one end of the load resistors 207 and 208 of the differential switch is connected to the second word line 212, the output signal of this differential switch swings with respect to the potential of the second word line. , "High" potential is the potential of the second word line, and "Low" potential is a potential that is lower than the potential of the second word line by the voltage drop across the load resistance due to the current of the differential switch.

This differential switch converts the level of the output signal of the memory cell S1 into a signal based on the second word line.

The output signal of this differential switch is the transistor line 209, 2 whose emitter is connected to the second data line 221, 222.
10 base, and this second data line 22
All read cells connected to 1.222 have the same structure. Further, the readout cells connected to the second data lines 226, 226 have the same structure, and each second theta line is connected to the emitter of a transistor, and this second data line is connected to a transistor whose emitter is connected. Inside,
The signal with the highest base potential is output. therefore,
By setting the second word line of the word to be read at a high potential, the data signal can be output to the second data line by setting the potential to be higher than the data signal of the word to be read.

As explained above, in a two-port storage device, the output signal of the storage cell S1 is level-converted into a signal based on the potential of the second word line, and this signal is sent to the terminal whose emitter is connected to the second bit line. By supplying the voltage to the base of the transistor and setting an arbitrary second word line to a high potential, a storage signal of an arbitrary word can be read out.

In addition, FIG. 2 is an explanatory diagram for the case of 2 ports,
1 bit cell M1 with storage cell S1 and read cell R1
However, it is clear that a multi-port storage device with an arbitrary number of ports can be realized by increasing the number of read cells having the same configuration in parallel with the read cell R1.

As can be seen from the effects of the invention, according to the present invention, a storage device with multiple ports can be realized with a simple circuit configuration, and especially when integrated circuits are used, it is possible to realize a semiconductor storage device with a small number of components and a small step size. can do.

Furthermore, since a multi-port storage device can be easily constructed using a bipolar semiconductor in which a transfer gate cannot be used, a high-speed multi-port semiconductor storage device that takes advantage of the high-speed performance of bipolar semiconductors can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a part of a memory cell of a conventional memory device, and FIG. 2 is a diagram showing an embodiment of the present invention in the case of two ports. S1-S4...Storage Senope R1-R4...see Read Senope 211, 215...1) First word line,
219°220.224---@1st bit line, 2
12,216-0@2nd word line, 221.222,2
26,226... Second bit line.

Claims (3)

[Claims] (1) A memory cell having a memory function connected to a first word line and a first bit line, and a memory cell to which a memory signal of the memory cell is input and connected to a second word line and a second bit line. a readout cell; A semiconductor memory device characterized in that second word lines are controlled separately. (2) The read cell has a transistor whose emitter is connected to the second bit line and a level conversion circuit, and the level conversion circuit adjusts the storage signal of the storage cell to a signal level based on the potential of the second word line. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is converted by a converter and supplied to the base of the transistor. (3) The collector of the level conversion circuit is impedance element 2! 2. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is constituted by a pair of differential transistors connected to the second word line via a pair of differential transistors whose emitters are commonly connected.