JPS6022798A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease the number of element and at the same time to attain a current read-out action by using a CMOS inverter, the 1st transfer MOS transistor (TR) connected to the gate of the CMOS inverter and the 2nd transfer MOS TR connected to the node of said CMOS inverter. CONSTITUTION:When data are written, the potential of the 1st word line 4 is set at a high level with the 1st transfer transistor 3 made conduct respectively. Then a node 5 is set at ''0'' by the function of a CMOS inverter 1 in case the data sent to a bit line 8 is set at ''1''. While the data of ''1'' is held at the node 5 in case the data of the line 8 is set at ''0''. In a read-out mode the potential of the line 4 is kept at a low level, and the potential of the 2nd word line 7 is set at a high level. Thus the 2nd transfer TR6 is conducted to transmit the data of the node 5 to the bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] This technology relates to memory cells used in semiconductor integrated circuits.

[Prior art and its problems]

Conventionally, a memory cell used in a memory device has constituted an array flop using six transistors. For this reason, it has been desired to achieve even higher integration by reducing the number of elements.

[Purpose of the invention]

It is an object of the present invention to provide a cell capable of current read operation without waiting for dynamic operation.

[Summary of the invention]

The present invention includes a CMOS inverter, a gt4i transfer MO8 transistor connected to the gate of the MO8 inverter, a first word line connected to the gate of the MOS transistor, and a node (5) of the CMOS inverter. ) connected to.

Second transfer MO8) transistor and this MO
S), a second word line connected to the gate of the F transistor; 2nd MOS) A semiconductor memory device comprising a bit line commonly connected to the other end of the transistor.

〔Effect of the invention〕

According to the present invention, it is possible to provide a novel memory cell capable of current reading with a small number of elements.

[Embodiments of the invention]

The memory cell for semiconductor integrated circuits provided by this technology is S0
MO8 inverter 1 and the first word iPi! connected to the first transfer transistor, such as the first transfer transistor 3 connected to the gate 2 of the CMOS inverter. 4, a second transfer transistor 6 connected to the node 5 of the CMOS inverter, a second word line 7 connected to the second transfer transistor, and a bit common to the first and second transfer transistors. It consists of a line 8.

Data writing and reading are performed as follows. When data is to be bitten, the potential of the first word line is set to a high level, and the first transfer transistor is made conductive. Then the data sent to the bit line becomes “
1", the node enters the rOJ state due to the operation of the CMOS inverter (during a write operation, the second position of the box of the second word line is set to low repeat
3 transfer transistors are in a cut-off state. ) Conversely, if the data sent to the bit line is "0", data "1" is held in the mate. In the case of a read operation, the potential of the first word line is kept low and the potential of the second word line is set to high level. Then, the second transfer transistor becomes conductive and the data of the node is transmitted to the bit line. Note that when writing and reading operations are not performed, the potentials of both the first and second word lines are set to a low level.

The memory cell of the present technology requires fewer transistors than a flip-flop type memory cell that requires six transistors. Furthermore, although the memory cell of the present technology is a dynamic operation cell, it can perform a read operation using a current, which is different from a conventional one-transistor, one-capacitor type dynamic memory cell.

[Brief explanation of drawings]

The drawings are circuit diagrams illustrating the invention in detail.

Claims (1)

[Claims] a CMOS inverter; a first transfer MOS transistor connected to the gate of the MO8 inverter; a first word line connected to the gate of the transistor; and a node of the CMOS inverter. (5) Second transfer Mc)S connected to
a second word line connected to the gate of the MOS transistor; A semiconductor memory device comprising a bit line commonly connected to the other end of a second MOS transistor.