JPS6346694A - Dynamic semiconductor memory device - Google Patents

Abstract

PURPOSE:To simultaneously attain a high speed and high grade integration by using a differential amplifier constituted of a CMOS type flip flop. a bipolar transistor and a MOS transistor as a bit line sense amplifier for reading the output data of a memory cell. CONSTITUTION:At the time of an active cycle from an initial potential, a node 15 is lowered, a column signal 9 is selecter after a while, and the differential amplifier is activated. Since the cell data is not transferred to the bit line at that time, an output determined by a base current passed by the transistors Q13-Q20 is outputted to output nodes 11, 12, thereafter, word lines rise, the data of the memory cell and a dummy cell is transferred to the bit line and a dummy bit line. When the different in the potential between the bit line and the dummy bit line goes to several +mV, a node is raised and the MOS flip flop is operated. When the difference in the potential between the bit line and the dummy bit line goes to about 0.5V, a node 15 is raised again and the BICMOS differential amplifier is operated.

Description

[Detailed description of the invention] C. Purpose of the invention] (Industrial application field) The present invention relates to a dynamic semiconductor memory device.

(Prior art) MO8 type semiconductor memory devices are becoming increasingly finer and faster.
In fields where high speed is required, such as the cache memory of large computers, 4 or 16 static RAMs (sRAMs) are currently widely used. However, as the gate length of MOS transistors progresses to miniaturization to about 0.5-degrees, external f
The fi source must be lowered, and it is no longer possible to increase the speed by miniaturization as in the past. Therefore, sRA
In M, a high speed ratio is achieved by introducing a bipolar transistor which has a larger current driving ability than a MOS transistor.

FIG. 3 shows an example of such an s RAM.The memory cell 21 is composed of a bistable circuit consisting of a MOS transistor QnztQ42 and load resistors R, , R2, and a MOS transistor Q43tQ44 as a transfer gate. It will be done. When the word line 23 is selected, bit @24.25 of the cell data is transferred, and when the column selection signal turns on MOS transistors Q4v and Q4°, the data of this bit, ii, 24.25 is transferred to I1.
Transferred to 0 line 26.27. l10t&26.27
The data for bipolar transistor T. , T22 as a driver, and is amplified by a sense amplifier 22 configured by connecting load resistors R, , R4. Q4. is a MOS transistor for activating the sense amplifier.

This kind of circuit configuration uses bipolar transistors and CMO
The combination with S element is called 810MO8.

In particular, the circuit configuration shown in FIG. 3 is called a differential amplifier, and utilizes the feature that the conductance g11 of the bipolar transistor is about 10 times larger than that of the CMO3 when a small signal is input. In other words, I10 wire 26.27 with large load capacity
Just by shaking it very small compared to CMO5,
Since the differential amplifier can operate at high speed, 810MO8
With the introduction of , SRAM can be made considerably faster. For example, when Hitachi's 64KSRAM is configured with only 2μ CMOS, the address access time tAA is 28.5ns.
On the other hand, when using 2μ 810MO8, t
AA speed is increased to 12.1 ns, about 42%.

(Problems to be Solved by the Invention) By the way, as shown in FIG. 3, sRAM has a memory cell made up of six elements, so compared to dynamic RAM (dRAM), which usually has a memory cell made up of four or fewer elements.
High integration cannot be achieved if the same gate length is used.For example, in order to achieve the same degree of integration, the gate length of sRAM must be 60 to 70% that of dRAM.

In other words, sRAM is suitable for increasing speed.

It has the essential drawback that it cannot be as highly integrated as dRAM, and the cache memory has been increased to 64, 256, and IM.
In the case of high integration, it is difficult to realize low cost per bit and high speed using sRAM.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a bit line sensor that amplifies memory data transferred to each bit line in a dynamic RAM in which a memory cell is configured by one MOS transistor and one capacitor. As an amplifier, a differential amplifier consisting of a CMOS flip-flop connected to the bit line directly or via a MOS transistor, and a BICMO3 connected to the bit line via a MOS transistor and the gate electrode of the MOS transistor. The problem was solved by using a configuration that combines both.

(Function) Since one MOS transistor and one capacitor are used in the memory cell, compared to sRAM where the memory cell is made up of 6 elements, it is possible to use 2 to 4 elements with the same design rule.
This enables twice as high integration.

Also, compared to non-destructive and current amplification type cells like sRAM cells, 810MO8 differential amplifier and dRA
In M, high speed was achieved by connecting a CMOS flip-flop, a differential amplifier composed of BICMO3, and a sense amplifier having both to the bit line. That is, rewriting of the destructive memory cell is performed by the 0MO8 flip-flop, and signal amplification of the memory cell output to the bit line is performed by the BICMO5 differential amplifier.

(Embodiment) FIG. 1 is an equivalent circuit showing a main part of a dRAM which is an embodiment of the present invention. A dRAM cell is used as the memory cell, which is currently the most suitable for high integration among memory devices and is composed of one transistor and one capacitor.

In Figure 1, a MOS transistor Ql and a capacitor C1 constitute a memory cell, Q2 and C2 constitute a dummy cell, and a node 1
A word line is connected to node 2, and a dummy word line is connected to node 2. However, since a one-transistor, one-capacitor memory cell is a destructive type and operates by voltage amplification, the bit line amplifies the data of the memory cell transmitted to the bit line. BI to sense amplifier
C: It is not possible to use only the MO8 differential amplifier. This is because the input impedance of the bipolar transistor used for the input of the B I CMOS differential amplifier is several hundred Ω.
Because it is very small, it is difficult to rewrite cell data to the memory cell, and the current consumption of the differential amplifier is very large, so the current consumption of the entire memory increases significantly (16
This is because M-bit dRAM reaches nearly 5 mA). Therefore, in FIG. 1, a flip-flop composed of MOS transistors Q3 to Q8 is used to rewrite (restore) a destroyed memory cell, and its input is connected to bit line 3 and dummy bit line 4. .

On the other hand, the memory cell signals output to bit line 3 and dummy bit line 4 are Q9. Through the QIO MOS transistor,
Enter the gates of Q13 and Q14, Qll, Q12.
The BICMO3 differential amplifier composed of Q17 to Q20 amplifies the signal at a high speed comparable to that of the sense amplifier of s RA'M. Q9 out of Q9-Q20. QIO, Q1
There are one set each of 3 to Q20 on the bit lines, Qll, Q1
There is only one 2 in each 10 lines. The output of the differential amplifier is connected to the I10 line node 11 and the dummy I10 line node 12.

The circuit operation of FIG. 1 is shown in FIG. 2. Here, consider the case where the cell data is 440 It. Bit line 3 in the precharge cycle. Dummy bit line 4 is precharged to a certain intermediate potential, at this time node 15 is rising and nodes 13 and 14 are set to a certain initial potential by transistors Q13-Q16. At the same time as the active cycle begins, node 15 is pulled down, and after a short time, column signal 9 is selected and the differential amplifier is activated. Since cell data has not yet been transferred to the bit line at that time, an output determined by the base currents flowing through transistors Q13-Q20 is output to output node 11.12. Thereafter, word lines 1 and 2 rise, and data in the memory cells and dummy cells are transferred to the bit lines and dummy bit lines. When the potential difference between the bit line and the dummy bit line reaches several tens of 111 V, node 8 is turned on and the CMOS flip-flop is operated. When the potential difference between the bit line and the dummy bit line reaches approximately O.SV, the node 15 is raised again to operate the BICMO8 differential amplifier. The CMOS flip-flop and BICMO8 differential amplifier are MOS transistors Q13. Because they are separated by Q14, the bit line data is not destroyed and the cell data is sent to the dummy 101iA11 and dummy 110m12 at the output node? %
It can be transferred quickly. Data is then rewritten into the memory cell using a CMOS flip-flop connected to the bit line. In other words, the bit line data becomes low level and the dummy bit line data becomes high level.

〔Effect of the invention〕

By using the present invention, it is possible to increase the density of dRAM and increase the density of BICMOS.
SRAM (7) High speed (0 MO8 (7) Mi (7)!
+! It is possible to achieve speeds that are about half that of the previous generation) at the same time.

In other words, as shown in Fig. 4, the bit line sense amplifier portion accounts for a fairly large proportion of the access time tRAC of the DRAM.
By converting to ICMOS, the access time is only increased to about 70% of that of 0MO8 only. Therefore, by using the present invention, which can also convert the bit line sense amplifier to BICMO3,
As shown in FIG. 4, the speed of tRAC can be increased to about half that of CMO5 alone. As mentioned before, B
Since ICMOS SRAM can increase the speed to about 42% of 0MO8 alone, the present invention has the effect that DRAM can achieve the same high speed as BICMOS SRAM.

Furthermore, in conventional dRAM sense amplifiers, the sensitivity is determined by the ratio CB/C3 of the bit line capacitance CB to the cell capacitance C8, and C8 cannot be set below 40 fv due to operating margins. In contrast, the present invention does not require Cs of 40fy to operate with current amplification, and can sufficiently operate with 20j'r or less. Currently, in high-density dRAMs of 4M or more, the memory cell process is complicated in order to secure Cs of 40fF or more, which leads to a decrease in yield or an increase in cost. In contrast, in the present invention, CS
207'r or less, there is no need to make the memory cell process so complicated, which has the advantage of lowering the cost per bit.

[Brief explanation of the drawing]

Figure 1.2 Circuit diagram of the bit line sense amplifier of the present invention, Part 2
Diagram: Diagram for explaining the timing chart of the present invention,
Figure 3: Circuit diagram of conventional BICMO8SRAM, Figure 4: Access time tRAG in 16MDRAM
FIG. 2 is a diagram for explaining details. 1 → word line, 2 → dummy word line, 3 → bit line, 4
→ dummy bit line, 7, 8 → CMOS flip-flop drive signal, 9 → input ram select signal, 13.14-)
B I CMOS differential amplifier Kugata signal. 114I10 line, 12→dummy I10 line, 15→bit line data transfer signal, C1, Q2→memory cell, C2, Q
2-+dummy cell, Q3~Q8-+CMOS flip-flop, Q9~Q20-)B ICMOS differential amplifier Im
. Agent Patent Attorney Nori Ken Yudo Takehana Kikuo Figure 1 Kano R4 Figure 2

Claims (3)

[Claims] (1) In a dynamic semiconductor memory device in which dynamic memory cells each consisting of one MOS transistor and one capacitor are arranged and formed on a semiconductor substrate, CMOS is used as a bit line sense amplifier for reading output data of the memory cells. 1. A dynamic semiconductor memory device characterized by using a differential amplifier composed of a type flip-flop, a bipolar transistor, and a MOS transistor. (2) The dynamic semiconductor memory device according to claim 1, wherein the differential amplifier is controlled by a column selection signal, and only those related to the selected column are activated. (3) The bit line of the CMOS type flip-flop is M
3. The dynamic semiconductor memory device according to claim 1, wherein the bit line and the differential amplifier are always separated from each other by being inputted to the differential amplifier through the gate of an OS transistor.