JPS5794822A - Input/output control system - Google Patents
Input/output control systemInfo
- Publication number
- JPS5794822A JPS5794822A JP55170541A JP17054180A JPS5794822A JP S5794822 A JPS5794822 A JP S5794822A JP 55170541 A JP55170541 A JP 55170541A JP 17054180 A JP17054180 A JP 17054180A JP S5794822 A JPS5794822 A JP S5794822A
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- input
- suck
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To prevent the hang of the software of a CPU, by holding the report of the switching the NOT READY state to the READY state until the report of the request for intervention through an input/output device. CONSTITUTION:A flip-flop 9 is set when the conditions are satisfied for all facts that an interface signal SVO is at an on-state, the unit check is given to the channel and that an intervention request is at an on-state, respectively. Then the flip-flop 9 is reset when a sense command is received and other conditions are all satisfied. With the setting and resetting of the flip-flop 9, +SUCK and -SUCK are turned on, respectively. A flip-flop 10 is set when -SUCK is turned on and an input/output device has been switched to the READY state. With the setting of the flip-flop 10, +RQi is turned on to be sent to a channel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170541A JPS6028018B2 (en) | 1980-12-03 | 1980-12-03 | Input/output control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170541A JPS6028018B2 (en) | 1980-12-03 | 1980-12-03 | Input/output control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5794822A true JPS5794822A (en) | 1982-06-12 |
JPS6028018B2 JPS6028018B2 (en) | 1985-07-02 |
Family
ID=15906808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55170541A Expired JPS6028018B2 (en) | 1980-12-03 | 1980-12-03 | Input/output control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6028018B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5998244A (en) * | 1982-11-26 | 1984-06-06 | Fujitsu Ltd | Printer |
-
1980
- 1980-12-03 JP JP55170541A patent/JPS6028018B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5998244A (en) * | 1982-11-26 | 1984-06-06 | Fujitsu Ltd | Printer |
JPS635767B2 (en) * | 1982-11-26 | 1988-02-05 | Fujitsu Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS6028018B2 (en) | 1985-07-02 |
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