JPS57130475A - Semiconductor memory storage and its manufacture - Google Patents
Semiconductor memory storage and its manufactureInfo
- Publication number
- JPS57130475A JPS57130475A JP1708281A JP1708281A JPS57130475A JP S57130475 A JPS57130475 A JP S57130475A JP 1708281 A JP1708281 A JP 1708281A JP 1708281 A JP1708281 A JP 1708281A JP S57130475 A JPS57130475 A JP S57130475A
- Authority
- JP
- Japan
- Prior art keywords
- poly
- substrate
- impurity
- shaped
- reproducibility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000005055 memory storage Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000012535 impurity Substances 0.000 abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 230000001668 ameliorated effect Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000005684 electric field Effects 0.000 abstract 1
- 239000002784 hot electron Substances 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To improve the reproducibility of the efficiency of writing and the characteristics of an EPROM by laminating and forming a floating gate and a control gate, introducing an impurity having the same conduction type as a substrate to a channel region from the end sections of the both gates and shaping source and drain regions. CONSTITUTION:A thin thermal oxide film 3, the poly Si floating gate 6, a thin thermal oxide film 4 of the surface of the poly Si 6 and the poly Si control gate 5 are laminated and formed to a region isolated by thick SiO2 on the substrate 1. The impurity layers 11, 12 having the same type as the substrate are shaped at high concentration from the opening sections of the source and drain regions in forms that are driven from the end sections of gate structure by approximately 0.5mum, and source and drain diffusion layers 7, 8 are molded. A metallic electrode and wiring 10 are connected and shaped through layer films 9, and a memory cell is formed. Accordingly, a drain electric field is concentrated, while hot electrons can be generated effectively and the efficiency of writing can be improved. The reproducibility of characteristics can be ameliorated because the distribution of the impurity of a strong field region can be shaped in excellent reproducibility through double diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1708281A JPS57130475A (en) | 1981-02-06 | 1981-02-06 | Semiconductor memory storage and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1708281A JPS57130475A (en) | 1981-02-06 | 1981-02-06 | Semiconductor memory storage and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57130475A true JPS57130475A (en) | 1982-08-12 |
Family
ID=11934048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1708281A Pending JPS57130475A (en) | 1981-02-06 | 1981-02-06 | Semiconductor memory storage and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57130475A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5147811A (en) * | 1990-03-13 | 1992-09-15 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the source/drain regions |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419372A (en) * | 1977-07-14 | 1979-02-14 | Nec Corp | Production of semiconductor memory |
-
1981
- 1981-02-06 JP JP1708281A patent/JPS57130475A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419372A (en) * | 1977-07-14 | 1979-02-14 | Nec Corp | Production of semiconductor memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5147811A (en) * | 1990-03-13 | 1992-09-15 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the source/drain regions |
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