JPS57120136A - Inhibiting system of input and output bus - Google Patents

Inhibiting system of input and output bus

Info

Publication number
JPS57120136A
JPS57120136A JP56003892A JP389281A JPS57120136A JP S57120136 A JPS57120136 A JP S57120136A JP 56003892 A JP56003892 A JP 56003892A JP 389281 A JP389281 A JP 389281A JP S57120136 A JPS57120136 A JP S57120136A
Authority
JP
Japan
Prior art keywords
signal
input
bus
gate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56003892A
Other languages
Japanese (ja)
Inventor
Akitoshi Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56003892A priority Critical patent/JPS57120136A/en
Publication of JPS57120136A publication Critical patent/JPS57120136A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

PURPOSE:To prevent the transmission of an erroneous signal to a computer system, by switching a gate circuit on an input/output bus which is driven by a power supply independent of an input/output device or a gate circuit within a bus drive adaptor. CONSTITUTION:A bus drive NAND gate 7 provided to a bus drive adaptor 3 functions as a line driver gate which expands the signal received from a process intput/output device 5 via an input/output bus 4 and a line receiver 32b and then transmits the signal to an input/output bus 2 of the CPU1 side. Furthermore the signal desired for the state of connection of a relay contact 64 of a relay circuit 6 is delivered to a signal line 8 connected to the gate 7. The gate 7 is switched by the signal supplied from the circuit 6 to inhibit the signal of the bus 4.
JP56003892A 1981-01-16 1981-01-16 Inhibiting system of input and output bus Pending JPS57120136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56003892A JPS57120136A (en) 1981-01-16 1981-01-16 Inhibiting system of input and output bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56003892A JPS57120136A (en) 1981-01-16 1981-01-16 Inhibiting system of input and output bus

Publications (1)

Publication Number Publication Date
JPS57120136A true JPS57120136A (en) 1982-07-27

Family

ID=11569829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56003892A Pending JPS57120136A (en) 1981-01-16 1981-01-16 Inhibiting system of input and output bus

Country Status (1)

Country Link
JP (1) JPS57120136A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5954354A (en) * 1982-09-22 1984-03-29 Fujitsu Ltd Signal transmitting method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5954354A (en) * 1982-09-22 1984-03-29 Fujitsu Ltd Signal transmitting method

Similar Documents

Publication Publication Date Title
JPS57120136A (en) Inhibiting system of input and output bus
JPS5614302A (en) Process control system
JPS56127201A (en) Centralized control system of mobile electric machinery
JPS57176850A (en) Transmitting system
JPS6479850A (en) Effective using method for bus
JPS5696562A (en) Connection circuit for transmission line
JPS54136144A (en) Shared input/output bus control unit
JPS5566192A (en) Remote control unit
JPS6461140A (en) Data transmission equipment
JPS55123704A (en) Maintenance device of control unit
JPS57101901A (en) Dispersion type control system
JPS57203133A (en) Power supply controller for terminal device
JPS6473447A (en) System for controlling low order device
JPS57176441A (en) Data transfer system
JPS57166623A (en) Channel device
JPS57138240A (en) Hairpin network
JPS5759221A (en) Dma transfer controlling system
JPS5725059A (en) Bus control system
JPS56152355A (en) Remote automatic power supply and break system
JPS5613856A (en) Signal transmitting system
JPS5785125A (en) Information processor
JPS5676801A (en) Plant control device
JPS56162167A (en) Switching system for dual computers
JPS5391639A (en) Power supply system in i/o interface circuit
JPS57139809A (en) Numerical control system