JPS5725059A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS5725059A
JPS5725059A JP9868980A JP9868980A JPS5725059A JP S5725059 A JPS5725059 A JP S5725059A JP 9868980 A JP9868980 A JP 9868980A JP 9868980 A JP9868980 A JP 9868980A JP S5725059 A JPS5725059 A JP S5725059A
Authority
JP
Japan
Prior art keywords
power supply
electric power
cpu block
function
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9868980A
Other languages
Japanese (ja)
Inventor
Toshio Mazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9868980A priority Critical patent/JPS5725059A/en
Publication of JPS5725059A publication Critical patent/JPS5725059A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Power Sources (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent an overall function stop of a system, by providing a means for rejecting the flow-in of an electric power supply from other CPU block in case when a self-CPU block has been disconnected from an electric power supply, on an interface, in a composite computer system. CONSTITUTION:CPU block 1A-1C constituting a composite computer system are provided with interfaces 5A-5C for communication and control. These interfaces 5A-5C are provided with not only a function for preventing the flow-in of an electric power supply from other CPU block through a system bus 3 or a control line 4 in a CPU block which has been disconnected from an electric power supply, but also a function by which the right of using of a system bus 3 is controlled without a hitch, therefore, even when disconnection of an electric power supply occurs in one CPU block, a function of other CPU blocks is performed normally.
JP9868980A 1980-07-21 1980-07-21 Bus control system Pending JPS5725059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9868980A JPS5725059A (en) 1980-07-21 1980-07-21 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9868980A JPS5725059A (en) 1980-07-21 1980-07-21 Bus control system

Publications (1)

Publication Number Publication Date
JPS5725059A true JPS5725059A (en) 1982-02-09

Family

ID=14226468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9868980A Pending JPS5725059A (en) 1980-07-21 1980-07-21 Bus control system

Country Status (1)

Country Link
JP (1) JPS5725059A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186006A2 (en) * 1984-12-27 1986-07-02 Kabushiki Kaisha Toshiba Multiprocessor system
JPS63155353A (en) * 1986-12-19 1988-06-28 Sony Corp Signal processor
WO1993006543A1 (en) * 1991-09-27 1993-04-01 Kabushiki Kaisha Toshiba Portable computer having function of switching over cpu clock

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186006A2 (en) * 1984-12-27 1986-07-02 Kabushiki Kaisha Toshiba Multiprocessor system
US5021950A (en) * 1984-12-27 1991-06-04 Kabushiki Kaisha Toshiba Multiprocessor system with standby function
JPS63155353A (en) * 1986-12-19 1988-06-28 Sony Corp Signal processor
WO1993006543A1 (en) * 1991-09-27 1993-04-01 Kabushiki Kaisha Toshiba Portable computer having function of switching over cpu clock

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