WO1993006543A1

WO1993006543A1 - Portable computer having function of switching over cpu clock

Info

Publication number: WO1993006543A1
Application number: PCT/JP1992/001219
Authority: WO
Inventors: Nobutaka Nakamura; Ryoji Ninomiya
Original assignee: Kabushiki Kaisha Toshiba
Priority date: 1991-09-27
Filing date: 1992-09-25
Publication date: 1993-04-01
Also published as: DE4244858A1

Abstract

A personal portable computer of a laptop or a notebook type, which can be driven by a battery and has a CPU (11), a clock oscillator (12) for feeding a clock to the CPU (11). To switch over the clock of the CPU (11) in the state the operation of the CPU (11) is ensured, the feed of a clock (CLK) is stopped in the state of the CPU (11) being reset, and thereby, the CPU (11) is set in a sleep mode. In the sleep mode, the consumption current of the CPU (11) is reduced largely because the clock (CLK) is stopped. When the CPU (11) is reset, the contents of the registers of the CPU (11) are saved. When the feed of the clock (CLK) is restarted and the reset signal is changed from an active state to an inactive one, the contents of the registers, which have been saved, are restored.

Description

Specification

Porter computer with a function to switch the port

The present invention relates to a laptop or notebook type personal portable computer, and more particularly to a portable computer having a CPU switching function.

Background technology

In recent years, various laptop or notebook type personal portable computers which are easy to carry and can be operated by a battery have been developed. In this type of portable computer, a sleep mode function is provided to automatically reduce the operating speed of the CPU under predetermined conditions in order to reduce unnecessary power consumption.

This sleep mode function is used, for example, when no keyboard operation is performed by the operator for a certain period of time.

Because the CPU in what is by connexion drive to the operating clock of the low-frequency O ₀

Such a sleep mode function is effectively used especially for a battery-powered portable computer.

However, the operation clock of the CPU is switched in this way. The conventional sleep mode function that can be applied is not applicable to all types of CPUs. This is because, depending on the system configuration of the microphone-port processor constituting the CPU, switching of the clock frequency may cause a malfunction in the CPU.

In particular, such as the microprocessor “i804486” developed and manufactured and sold by Intel Corporation, and the “TransPu Isetu” microprocessor developed and manufactured and sold by Inmos Corporation. When using a microprocessor that operates at a clock faster than the external clock supplied from the CPU as a CPU, there is a high risk that malfunctions will be caused by clock switching. This is for the following reasons.

In other words, such a processor has an internal oscillator including a PLL circuit, generates a high-speed clock synchronized with a clock supplied from the outside by the PLL circuit, and realizes a high-speed operation by using the clock. I have. Therefore, in order for such a microprocessor to operate normally, the phase of an externally supplied clock must be stable. Otherwise, an error occurs in the synchronous operation of the PLL circuit.

Therefore, if the conventional sleeve mode function is applied to the CP を持つ having the internal oscillator including the PLL circuit as it is, the discontinuity of the clock phase when switching the clock frequency causes Therefore, the operation of C ϋ なく is not guaranteed. Clock frequency switching is used not only for the purpose of power saving by the sleep mode, but also for the purpose of ensuring the compatibility of computer systems.

That is, ablation software or hardware that is configured to run at a slow clock may not be available under a CPU running at a high speed clock. In this case, the CPU is normally operated with a high-speed clock, and the CPU is operated with a low-speed clock only when using these specific application software. It is necessary to use such a form of use.

Clock switching for the purpose of ensuring compatibility is also similar to clock frequency switching in the case of sleep mode, as described above. When applied to a CPU with an oscillator, there is a problem that the operation of the CPU cannot be guaranteed.

Therefore, the present invention enables the frequency of the clock supplied to the CPU to be switched while guaranteeing the operation of the CPU, and is suitable for reducing power consumption and ensuring compatibility with low-speed systems. The purpose is to provide a computer. Disclosure of the invention

According to a first aspect of the present invention, a port tab having a CPU, a clock generation circuit for supplying a clock to the CPU, and various peripheral circuits connected to the CPU via a system bus Determining whether a predetermined mode setting condition for setting the CPU into the sleep mode is satisfied, and responding to the satisfaction of the condition, storing the data of the register of C C in a memory. An evacuation unit; and, in response to the evacuation of the data, resetting the CPU by setting a reset signal supplied to the CPU to an active state, and resetting the clock. Clock stop means for stopping supply, and in response to an interrupt request from the peripheral circuit to the CPU, for restarting the supply of the mouth and for restarting the CPU. Means for setting the reset signal to an inactive state; A portable computer provided with means for returning data from the memory to the CPU in response to the setting of the inactive state of the set signal.

In this portable computer, the supply of the clock is stopped when the CPU is reset, so even if the clock is stopped to reduce power consumption, the CPU stops the clock. Is not affected at all. When the CPU is reset, the data of that CPU is saved. The saved data is returned to the CPU when the clock supply is restarted and the reset is released. Therefore, CPU operation can be started from the state before the clock was stopped. Therefore, a new sleep mode function of stopping the operation of the CPU while guaranteeing the operation of the CPU can be realized, and the power consumption of the portable computer can be sufficiently reduced. It becomes possible. According to a second aspect of the present invention, a port tab having a CPU, a clock generation circuit for supplying a clock to the CPU, and various peripheral circuits connected to the CPU via a system bus A computer that determines whether a predetermined mode setting condition for setting the CPU in the sleep mode is satisfied, and stores the data of the register of the CPU in the memory in response to the satisfaction of the condition. Evacuation means, and in response to the evacuation of the data, resetting the CPU by setting a reset signal supplied to the CPU to an active state, and supplying power to the CPU. Power supply stopping means for stopping, and in response to an interrupt request from the peripheral circuit to the CPU, power supply to the CPU is restarted, and the reset signal is set to an inactive state. Therefore, a portable computer having means for restarting the CPU and means for returning data from the memory to the CPU in response to the setting of the reactive state of the reset signal is provided. Provided.

In this portable computer, since the power of the CPU is turned off when the CPU is reset, the power consumption of the CPU can be sufficiently reduced without affecting the operation of the CPU. You. When the CPU is reset, the data of the register of the same PU is saved. The saved data is returned to the CPU when the power is turned on and the reset is released. Therefore, CPU operation can be started from a state before the power is turned off. Therefore, A new sleep mode function of stopping power supply to the CPU while guaranteeing the operation of the CPU can be realized, and the power consumption of the data processing device can be significantly reduced.

According to a third aspect of the present invention, a CPU, various peripheral circuits connected to the CP via a system bus, and a first clock and a second clock having a lower frequency than the first clock are generated. A portable computer having a clock generation circuit, determining whether a predetermined mode setting condition for setting the CPU to the sleep mode is satisfied, and responding to the satisfaction of the condition. Means for saving the data of the register to the memory, and resetting the CPU by setting the reset signal supplied to the CPU to active in response to the first timing signal. Reset means, a first clock switching means for switching a clock supplied to the CPU from the first clock to the second clock in response to a second timing signal, and the data Evacuation of A first delay circuit for generating the first timing signal in response and generating the second timing signal by delaying the first timing signal by a predetermined time; A second clock switching means for switching a clock supplied to the CPU from the second clock to the first clock in response to a third timing signal; and a fourth timing signal. Reset reset means for restarting the CPU by setting the reset signal to an inactive state in response to the reset signal, and an assignment from the peripheral circuit to the CPU. A second timing signal in response to the read request, and generating the fourth timing signal by delaying the third timing signal by a predetermined time. And a means for returning data from the memory to the CPU in response to setting of the reset state of the reset signal.

In this portable computer, the first clock of high frequency and the second clock of low frequency are selectively used as the CPU clock, and the clock switching is performed by resetting the CPU. It is performed in the state where it was done. In this case, the time from when the CPU is reset to when the clock is switched from the first clock to the second clock is defined by the delay time of the first delay circuit. In addition, the time from when the clock is switched to the second clock or the first clock until the reset signal is set to inactive is defined by the delay time of the second delay circuit. You. Therefore, by setting the delay time of these delay circuits, appropriate timing control according to the specifications of the CPU can be performed. Therefore, the operation speed of the CPU can be switched while the operation of the CPU is guaranteed, and a portable computer with excellent compatibility and power saving can be realized. ₍ According to the fourth aspect of the present invention, A portable computer having a CPU driven at an operation speed according to a clock supplied from outside, comprising: a voltage-controlled oscillator whose oscillation frequency is variably set in accordance with a control voltage; and a clock from the CPU. Before being supplied to the voltage controlled oscillator in response to a lock switching request And a voltage control means for increasing or decreasing the value of the control voltage, wherein a portable computer is provided in which the oscillation output of the voltage controlled oscillator is supplied to the CP as the clock.

In this portable computer, the oscillation output of the voltage-controlled oscillator is used as the operation clock of the CPU, and the operation clock is controlled by variably setting the oscillation frequency of the voltage-controlled oscillator. Switch from high-speed clock to low-speed clock. In this case, since the frequency of the oscillation output of the voltage-controlled oscillator changes gradually and continuously, the operation clock of the CPU does not instantaneously switch from the high-speed clock to the low-speed clock. Therefore, problems such as phase discontinuity when the clock switches from the high-speed clock to the low-speed clock can be solved, and the operation of the CPU can be guaranteed. Therefore, the clock of the CPU can be switched while the operation of the CPU is guaranteed, so that the power consumption and compatibility of the portable computer can be reduced.

According to a fifth aspect of the present invention, there is provided a portable computer having a CPU capable of switching between a normal operation mode and a low current consumption mode, wherein an interrupt request is periodically issued in a first cycle. First timer means for generating an interrupt request; second timer means for periodically generating an interrupt request in a second cycle longer than the first cycle; and an interrupt from the first or second timer means. Means for generating a timer interrupt signal for switching the CPU from the low current consumption mode to the normal mode in response to the request; When the CPU is in the low current consumption mode, the CPU is set to the low level so that interrupts and requests of the first timer means are prohibited and interrupt requests of the second timer means are permitted. A portable computer comprising: interrupt mask means for selectively masking an interrupt request of the first timer means according to a current consumption mode or the normal operation mode. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a system configuration of a portable computer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a specific configuration of a clock control circuit provided in the system of the first embodiment.

FIG. 3 is a flowchart for explaining an operation of shifting to a sleep mode in the system of the first embodiment.

FIG. 4 is a flowchart illustrating a return operation from a sleep mode in the system of the first embodiment.

FIG. 5 is a timing chart showing the operation timing of the system of the first embodiment.

FIG. 6 is a block diagram showing another example of the specific configuration of the clock control circuit provided in the system of the first embodiment.

FIG. 7 is a flowchart for explaining another example of the operation of shifting to the sleep mode in the system of the first embodiment.

FIG. 8 is a flowchart for explaining another example of the return operation from the sleep mode in the system of the first embodiment.

FIG. 9 is a portable computer according to a second embodiment of the present invention. —A block diagram showing the evening system configuration.

FIG. 10 is a block diagram showing an example of a specific configuration of a bus controller provided in the system of the second embodiment.

FIG. 11 is a flowchart for explaining an operation of shifting to a sleep mode in the system of the second embodiment.

FIG. 12 is a flowchart for explaining a return operation from the sleeve mode in the system of the second embodiment.

FIG. 13 is a timing chart showing the operation timing of the system of the second embodiment.

FIG. 14 is a block diagram showing another specific configuration example of the bus controller provided with the system of the second embodiment.

FIG. 15 is a flowchart for explaining another example of the transition operation to the sleep mode in the system of the second embodiment.

FIG. 16 is a flowchart for explaining another example of the return operation from the sleeve mode in the system of the second embodiment.

FIG. 17 is a block diagram showing a system configuration of a portable computer according to a third embodiment of the present invention.

FIG. 18 is a timing chart for explaining the operation of the timing control circuit provided in the system of the third embodiment.

FIG. 19 is a flowchart illustrating the operation of shifting to the sleep mode in the system of the third embodiment.

FIG. 20 is a flowchart for explaining an operation of returning from a sleep mode in the system of the third embodiment.

FIG. 21 is a flowchart for explaining the overall operation flow at the time of clock switching in the system of the third embodiment. FIG. 22 is a block diagram illustrating a modified example of the timing control circuit provided in the system of the third embodiment.

FIG. 23 is a timing chart illustrating the clock switching operation performed by the timing control circuit shown in FIG. 22 to the high-speed clock power or the low-speed clock.

FIG. 24 is a timing chart illustrating a clock switching operation from a low-speed clock to a high-speed clock, which is performed by the timing control circuit shown in FIG.

FIG. 25 is a flowchart for explaining another example of the operation of shifting to the sleep mode in the system of the third embodiment.

FIG. 26 is a flowchart for explaining another example of the return operation from the sleep mode in the system of the third embodiment.

FIG. 27 is a block diagram showing a system configuration according to a fourth embodiment of the present invention.

FIG. 28 is a timing chart for explaining the clock switching operation from the high-speed clock to the low-speed clock in the system of the fourth embodiment.

FIG. 29 is a timing chart for explaining the clock switching operation from the low-speed clock to the high-speed clock in the system of the fourth embodiment.

FIG. 30 is a block diagram showing a first configuration example of a voltage switching circuit provided in the system of the fourth embodiment.

FIG. 31 is a block diagram showing a second configuration example of the voltage switching circuit provided in the system of the fourth embodiment.

Fig. 32 shows the voltage cutoff provided in the system of the fourth embodiment. FIG. 9 is a block diagram showing a third configuration example of the replacement circuit.

FIG. 33 is a timing chart showing an example of a clock switching operation in the system of the fourth embodiment.

FIG. 34 is a timing chart showing another example of the clock switching operation in the system of the fourth embodiment.

FIG. 35 is a block diagram showing a system configuration according to a fifth embodiment of the present invention.

FIG. 36 is a flow chart for explaining a transition operation to the CPU sleep mode and a return operation from the CPU sleep mode in the fifth embodiment.

FIG. 37 is a diagram showing an example of the configuration of a first RTC register provided in the system of the fifth embodiment.

FIG. 38 is a diagram showing an example of the configuration of a second RTC register provided in the system of the fifth embodiment.

FIG. 39 is a diagram showing an example of the configuration of a first interrupt mask register provided in the system of the fifth embodiment.

FIG. 40 is a diagram showing an example of a configuration of a second interrupt mask register provided in the system of the fifth embodiment.

FIG. 41 is a diagram showing an example of a specific configuration of the interrupt controller provided in the fifth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a system configuration of a portable computer according to a first embodiment of the present invention. This portable A computer is a computer that is powered by AC commercial power or a battery that is removably attached to the computer itself. The CPU (central processing unit) 11, clock oscillator 12, clock control circuit 13 , Dynamic RAM (DRAM) 14, real-time clock (RTC) 15, system timer 16, power supply 17 for knock-up, keyboard controller (KBC) 18, and programmable interrupt controller (PIC) 19,

The CPU 11 controls the entire system. The components, namely, the clock control circuit 13, the dynamic RAM (DRAM) 14, and the real-time clock ( RTC) 15 and system timer 16, keyboard controller (KBC) 18, and programmable interrupt controller (PIC) 19. The CPU 11 includes, for example, the microprocessor 80486 described above, and includes an internal oscillator 11 including a PLL circuit in order to internally generate a high-speed clock. In other words, the CPU 11 internally generates a clock several times the clock CLK supplied via the clock control circuit 13 by the internal oscillator 111, and uses the clock to operate at high speed. It is a configuration to do.

In addition, the CPU 11 executes a BIOS (Basic Input Output System) program, which is correlated by the application program being executed, to determine whether or not the sleep mode setting condition is set. Judgment, when the condition is satisfied, CPU 11 Performs the save processing of the register contents in 1, the setting processing of sleeve mode identification information (clock stop flag) indicating transition to the sleep mode, and the execution of the Ha1t instruction in order. The condition for setting the sleep mode is satisfied, for example, when the operator has not performed a key input operation for a certain period of time or the like.

The data of each register of the CPU 11 is saved in the dynamic RAM (DRAM) 14. The sleep mode identification information (clock stop flag) is stored in the memory in the real time clock (RTC) 15.

When the CPU 11 executes the H a 1 t instruction for stopping the execution of the program, the CPU 11 sets the signal MZ I 0 to “L” to notify that the CPU 11 has been set to the halt state. "Set the level, signal DZC to level, and signal WZR to level. Here, the signal MZI0 is a status signal indicating whether to access the memory or the I / O device, and the control signal DZC is a status signal indicating whether to output data or a command. Yes, the signal WZR is a status signal indicating whether to perform a write or a read.

Clock oscillator 12 generates clock CLK. The frequency of this clock CLK is, for example, 32 MHz or 16 MHz. The clock CLK from the clock oscillator 12 is supplied to CPU 11 under the control of the clock control circuit 13.

Clock control circuit 13 supplies clock CLK :, reset signal RESET, and interrupt signal INT to CPU 11 I do. The clock control circuit 13 normally supplies the clock CLK to the CPU 11 in order to operate the CPU 11, but when the CPU 11 is in the sleep mode, the clock CLK is supplied to the clock control circuit 13. Clock supply of CLK is stopped. Further, the clock control circuit 13 activates the reset signal RESET before stopping the clock CLK, thereby setting the CPU 11 to the reset state. While the reset signal RESET is active (that is, while the CPU 11 is in the reset state), the execution of instructions by the CPU 11 and the activation of the system bus 10 by the CPU 11 do not occur.

The reason why the supply of the clock CLK is stopped after the CPU 11 is reset as described above is that the CPU 11 stops supplying the clock CLK due to a clock phase shift caused by the stop of the clock CLK supply. This is to prevent malfunction.

The state in which the CPU 11 can enter the sleep mode means that the signals MZ IO, D / C, and WZR from the CPU 11 are set to "L", "L", and "H". Recognized by o

That is, when it becomes possible to shift to the sleep mode, as described above, the CPU 11 executes the Ha1t instruction, and sets the signal MZIO to the “L” level, the signal DZC to the “L” level, Issue WR to "H" level. For this reason, the clock control circuit 13 detects that the levels of these signals enable the CPU 11 to enter the sleep mode. When the clock control circuit 13 receives the hardware interrupt request IRQ from the interrupt controller 19, the clock control circuit 13 returns the CPU 11 from the sleep mode to the normal operation mode. Is performed. That is, the clock control circuit 13 first restarts the supply of the clock CLK, and then makes the reset signal RESET inactive so that the operation of the CPU 11 is restarted. After that, the clock control circuit 13 supplies the CPU 11 with the interrupt signal INT.

The dynamic RAM (DRAM) 14 is for storing an application program executed by the CPU 11 and the like, and when transitioning to the sleep mode, the dynamic RAM (DRAM) 14 is used. The data of each register of CPU 11 is saved to

The real-time clock (RTC) 15 is a module for realizing a clock function and power rendering function. Its internal memory is used for backup so that its stored contents are not lost even when the power is turned off. Power supply 17 is always supplied. The memory of the real-time clock (RTC) 15 stores the sleep mode identification information (clock stop flag) described above.

The sleep mode identification information (clock stop flag) indicates whether the CPU 11 has returned from sleep mode to normal mode or the system power. Used to identify if it was turned on. That is, the transition from the active state of the reset signal RESET to the active state is performed by the CPU. 11 occurs not only when returning from sleep mode to normal mode, but also when the system is turned on. At power-on, the saved data need not be restored to the CPU 11 registers just by performing normal bootstrap processing, but when returning from sleep mode, the register contents are restored.

It is necessary to return to CPU11. For this reason, when the reset signal RESET changes from the active state to the active state, the CPU 11 recognizes the sleep mode identification information (clock) of the real-time clock (RTC) 15. Check the stop flag) to determine whether or not it is a return from sleep mode.

The real-time clock (RTC) 15 periodically generates a timer interrupt request IRQ8 at a cycle of, for example, 500 ms. This timer interrupt request IRQ 8 is supplied to the interrupt controller 19.

The system timer 16 is a timer that periodically generates a timer interrupt request IRQ0 at a period of, for example, 55 ms. This timer interrupt request IRQ0 is supplied to the interrupt controller 19.

The keyboard controller (KBC) 18 is a barrel that controls the keyboard built into the portable computer itself. It scans the keyboard's keyboard matrix and stores key data corresponding to the pressed key. (Scan code). At this time, the keyboard controller (KBC) 18 sends a key input to notify the CPU 11 of the key input. Request IRQ 1 is generated. This key input interrupt request

IRQ 1 is supplied to the interrupt controller 19.

Interrupt controller 19 is a hardware interrupt request.

Supply IRQ to clock control circuit 13 to CPU11. That is, the interrupt controller 19 sends a timer interrupt request.

When one of IRQ0, key input interrupt request IRQ1, and timer interrupt request IRQ8 is received, a hardware interrupt request IRQ is generated. In this case, the timer interrupt request

One of IRQ0 and the timer interrupt request IRQ8 can be selectively masked by the interrupt mask register in the interrupt controller 19.

FIG. 2 shows an example of a specific configuration of the clock control circuit 13. As shown in the figure, the clock control circuit 13 includes a clock switching circuit 131, a reset signal generation circuit 132, an interrupt signal generation circuit 133, and an RS flip-flop 135. Is configured.

The clock switching circuit 13 1 selects and outputs either the clock CLK or the GND level output, and the flip-flop 135 is reset when the power is reset. Stops the clock CLK supply to CPU 11 by outputting the level. On the other hand, when the flip-flop 135 is set strongly, the clock switching circuit 1331 selects the clock CLK and supplies it to the CPU 11.

The gate circuit 134 sets the signals MZ IO, DZC, and WZR to level, level, and level, respectively. When the CPU 11 recognizes that the instruction has executed the Ha1t instruction, it resets the flip-flop 1335. The flip-flop 1335 is set by a hardware interrupt request IRQ from the interrupt controller 19 0

The reset signal generating circuit 132 responds to the output of the gate circuit 134 for resetting the flip-flop 135 and activates the reset signal RSET. Further, the reset signal generation circuit 132 sets the reset signal RSET to inactive in response to the interrupt request IRQ. The interrupt signal generating circuit 133 generates an interrupt signal INT in response to the interrupt request IRQ.

When the clock control circuit 13 detects that the signals MZI0, DZC, and WZR have been set to the “L” level, the level, and the “H” level, respectively, The reset signal RESET is set to the active state by the output, and the output of the clock switching circuit 13 1 is switched from the clock CLK to GND by resetting the flip-flop 135. . In this state, when an interrupt request IRQ is input, the flip-flop 135 is set, the output of the clock switching circuit 131 is switched from GND to clock CLK, and the clock is switched to clock CLK. After the switching—After a fixed time (for example, 1 ms) has elapsed, the reset signal RESET is set to inactive. Then, an interrupt signal INT is generated from the interrupt signal generating circuit 133. Next, the transition operation to the sleep mode and the return operation from the sleep mode in the pop-up menu in FIG. 1 will be described with reference to FIGS.

First, with reference to the flowchart of FIG. 3, an operation in a case where the clock CLK of the CPU 11 is stopped in the sleep mode will be described.

When the CPU 11 waits for a key input during execution of an application program, for example, usually, an interrupt waiting function routine as shown in Fig. 3 is called by the application program. Is done. The function waiting for the interrupt is provided by the BIOS program. In the interrupt waiting function routine, first, the CPU 11 determines whether or not a key input interrupt has occurred (step S11). This judgment process is executed by the CPU 11 checking the cause of the interrupt when the interrupt signal INT is supplied to the CPU 11. Whether or not the interrupt is caused by the key input interrupt request IRQ1 is determined, for example, by reading the status register of the interrupt controller 19. When a key input interrupt occurs, the CPU 11 reads the key code from the keyboard controller (KBC) 18 (step S12), and then returns to the execution of the application program.

On the other hand, if no key input interrupt has occurred, the CPU 11 recognizes that the sleep mode setting condition has been satisfied, and executes the subroutine for setting the sleep mode. Run. Here, the CPU 11 first saves the contents of the register at that time in the dynamic RAM (DRAM) 14 (step S13). Next, the CPU 11 stores the sleep mode identification coast information (clock stop flag) of “1” in the memory 15 of the real-time clock (RTC) (step 11). Top S14). Thereafter, the CPU 11 executes the Ha1t instruction (HLT) for stopping the operation (step S15). This Halt instruction prevents the use of the same 1111 <system bus 10.

When the CPU 11 executes the Ha1t instruction, the signal MZI 0 is set to “L”, the signal DZC is set to “L”, and the signal Set WZR to "H". And maintain Ha1t unless restarted o

The clock control circuit 13 monitors these signals (M / I0, D / C, WZR). When it is found that the CPU 11 has executed the HALT instruction, the clock control circuit 13 is reset. Set the RESET signal to active to reset CPU11. When the reset RESET signal becomes active, all operations of CPU11 are terminated. Thereafter, the clock control circuit 13 stops supplying the clock CLK to CPU 11. As a result, CPU 11 enters a sleep mode in which the supply of clock CLK is stopped.

Thereafter, the clock control circuit 13 responds to the hardware interrupt request IRQ from the interrupt controller 19, and The supply of lock CLK is restarted, and after about 1 ms, the reset signal RESET is changed from active to inactive. As a result, the reset signal RESET is kept active until about lms has elapsed since the supply of the clock CLK was restarted. The reason why the reset signal RESET is kept active for a certain period of time after the supply of the clock CLK is restarted is to ensure the proper operation of the CPU 11.

When the reset signal RSET transitions to inactive, the CPU 11 starts operation, initializes internal registers, and fetches instructions from a specific address. Thereby, the routine of FIG. 4 is executed. The routine shown in Fig. 4 is executed when the reset switch for forcibly setting CPU1] to the initial state is turned on or when the power is turned on.

In the routine shown in FIG. 4, the CPU 11 first sets the contents of the sleep mode identification information (mouth stop flag) stored in the real time clock (RTC) 15 memory. Is checked (step S21). If the sleep mode identification information (clock stop flag) power is “0”, the CPU starts up normally because the power is turned on or the reset switch is turned on instead of returning from sleep mode. 1 executes bootstrap processing (step S22). In this bootstrapping process, initialization of peripheral circuits, activation of an operating system, and the like are performed.

— Sleep mode identification information (clock stop flag) If the value is "1", the CPU 11 returns from sleep mode, and the CPU 11 uses the real-time clock (RTC) 15 sleep mode identification information (clock stop). Flag) to “0” (step S23), and then the saved register contents are read from the dynamic RAM (DRAM) 14 into the internal register, and the contents of that register are used as the basis. Return (step S24). Then, the CPU 11 shifts to the key input interrupt check processing (step S11) described with reference to FIG. 3, and thereby returns to the state before the sleep mode was set.

As described above, the sleep mode function of this embodiment stops the clock CLK while the CPU 11 is reset, and stops the clock CLK. Has been reduced.

FIG. 5 shows the operation timing of the sleep mode operation described above. As shown in the figure, when shifting from the normal mode to the sleep mode, first, the Ha1t instruction is executed by the CPU 11, and in response to this, the reset signal RESET is reset. The signal is activated "high", which resets the CPU. Then, after this, the supply of the clock CLK is stopped in a state where the CPU 11 force is reset.

When returning from the sleep mode to the normal mode, the supply of the clock CLK is first restarted in response to the hardware interrupt request IRQ. After that, the reset RESET signal is made inactive, which causes The operation of the CPU 11 is resumed.

Next, an example of another specific configuration of the clock control circuit 13 will be described with reference to FIG.

The clock control circuit 13 in FIG. 2 indicates that the CPU 11 can be stopped by the signals (MZI0, DZC :, WZR) output by executing the Ha1t instruction. In other words, the clock control circuit 13 ′ in FIG. 6 recognizes that the saving of the register has been completed. However, the clock control circuit 13 ′ in FIG. It is a configuration that recognizes that

That is, the clock control circuit 13 includes a decoder 201 and a register 202 instead of the gate circuit 134. The decoder 201 decodes the address from the CPU 11 and sets a predetermined 1-bit notification data on the bus 10 to the register 202 when the address has a predetermined value. When the notification data is set in the register 202, the reset RESET signal is activated by the reset signal generation circuit 132, and the flip-flop 135 is reset. The supply of CLK is stopped.

By using the clock control circuit 13 'with such a configuration, even if the CPU 11 does not execute the Ha It instruction, the CPU 11 can finish register saving and stop the clock. It becomes possible to recognize that the state has been reached.

As described above, in the portable computer of the first embodiment, the CPU 11 is reset and the clock is reset. Since the supply of the clock CLK is stopped, it is possible to prevent a situation in which the CPU 11 malfunctions due to the stop of the clock CLK. In addition, since the clock CLK is stopped instead of lowering the clock CLK frequency as in the normal sleep mode, the power consumption can be greatly reduced.

In addition, when the CPU 11 is reset, the contents of the registers of the CPU 11 are saved, the supply of the clock CLK is restarted for the saved contents of the registers, and the reset is set to inactive. Will be restored at the time. Therefore, the operation of CPU 11 can be started from the state before the clock CLK is stopped, and the normal operation of CPU 11 can be reliably ensured.

Although such a clock switching system is particularly suitable for realizing the sleep mode function of a CPU having an internal oscillator, it does not have an internal oscillator including a PLL circuit and synchronizes with an external clock. Even if it is applied to a working CPU, the power consumption can of course be reduced without causing a malfunction.

Further, in the first embodiment, the sleeve mode identification information is software-controlled by the CPU 11 in order to identify whether the CPU 11 has returned from the sleep mode or the system has been turned on. However, for example, it is also possible to prepare a flip-flop or the like in the clock control circuit 13 and set sleep mode identification information in a hardware manner in this flip-flop.

In addition, in order to maintain the sleep mode for a long time, the system timer interrupt request IRQ during the sleep mode is required. 0 is preferably masked by the interrupt controller 19. In this way, the system timer interrupt request IRQ0 generated in units of 55 ms is prohibited. For this reason, the sleep mode period can be set to 55 ms or more, and power consumption can be further reduced.

In this case, the processing of cipui 1 when shifting from the normal mode to the sleep mode is performed as shown in FIG.

That is, in this case, step S100 and step S101 are added to steps S13 to S15 of the subroutine for the sleep mode transfer shown in FIG. . In step S100, CP P11 sets the timer interrupt period of the real-time clock (RTC) 15 to 500 ms. This is realized by writing data indicating 500 ms to a predetermined register in the real-time clock (RTC) 15. In step S101, CP # 11 disables the timer interrupt of system timer 16 and enables the timer interrupt of real-time clock (RTC) 15. This is realized by writing a predetermined mask data into the interrupt mask register of the interrupt controller (PIC) 19.

As a result, in sleep mode, the system timer interrupt request IRQ 0 generated in 55 ms units is disabled, and the real-time clock (RTC) 15 timer interrupt request IRQ 8 generated in 500 ms units is disabled. Is allowed. For this reason, the sleep mode setting period can be set to 55 ms or more, Power consumption can be further reduced.

The reason for setting the timer interrupt cycle of the real-time clock (RTC) 15 to 500 ms here is to support the clock function of the application program. In other words, if you are running an application program that has the function of displaying the time digitally on the display screen, it is necessary to update the timer count at least within .1 s. You. For this reason, the maximum setting period of the sleep mode is limited to 500 ms by using a timer interrupt in units of 500 ms.

Also, when the system timer interrupt request IRQ 0 is disabled and the mode shifts to the sleep mode, the processing of the CPU 11 for shifting from the normal mode to the sleep mode is performed in the following manner. This is done as shown in Figure 8.

That is, in this case, step S102 is performed in addition to steps S23 and S24 shown in FIG. In step S102, CPU]] enables the timer interrupt of the system timer 16 and disables the timer interrupt of the real-time clock (RTC) 15. This is realized by writing predetermined mask data to the interrupt mask register of the interrupt controller (PIC) 19. Thus, in the normal mode, timer interrupts in units of 55 ms are enabled.

Hereinafter, a second embodiment of the present invention will be described.

FIG. 9 shows a portable computer according to a second embodiment of the present invention. The system configuration of the computer is shown. The portable computer according to the second embodiment is configured to stop supplying power to the CPU in the sleep mode.

That is, this portable computer is a computer driven by an AC commercial power supply or a battery which is detachably attached to the main body of the computer. As shown in the figure, the CPU 11A and the switch circuit 12 are connected. A, controller 13 A, R0M 14 A, dynamic RAM (DRAM) 15 A, real-time clock (RTC) 16 A, keyboard controller Controller (KBC) 17 A, power supply circuit 18 A, AC power adapter 19 A, battery 20 A, backup power supply 21 A, clock switching circuit 22 A, clock oscillator 23 A, programmable interrupt controller It has a 24 A troller (PIC) and 25 A system timer.

CPU 11A Controls the entire system and controls the components that make up the peripheral circuits via the system bus 1Ob, i.e., R0M14A, dynamic 15 A RAM (DRAM), 16 A real-time clock (RTC), 17 A keyboard controller (KBC), 24 A interrupt controller (PIC), and Connected to system timer 25A. This CPU 11A is composed of, for example, a microprocessor (80486) and has an internal oscillator 11A including a PLL circuit to generate and operate a high-speed chip internally. ing. In other words, the CPU 11A receives the clock via the clock switching circuit 22A. In this configuration, a high-speed clock several times higher than the clock CLK supplied from the clock oscillator 23A is internally generated by the internal oscillator 11A, and high-speed operation is performed by using the generated clock.

In addition, the CPU 11A determines whether or not a sleep mode setting condition has been established by executing a BI 0 S (Basic Input Output System) program called by the running application program. When the condition is satisfied, the CPU sequentially saves the data of each register in the CPU 11A, sets the sleep mode identification flag indicating that the mode is shifted to sleep mode, and executes the Halt instruction. Do. The sleep mode setting condition is satisfied, for example, when a key input operation by an operator has not been performed for a certain period of time.

The data of the CPU11A register is saved to the dynamic RAM (DRAM) 15A. The sleep mode identification flag is stored in a memory inside the real-time clock (RTC) 16A.

When the CPU 11A executes the Ha1t instruction to stop program execution and bus access, the CPU 11A notifies the CPU 11A that it has been set to the halt state. Set signal M / I0 to "L" level, signal DZC to level, and signal WZR to "H" level. Here, as described above, the signal M0 indicates whether to access the memory or the input / output device, and the signal DC indicates whether to output the data or the command. The signal WZR indicates whether to perform writing or reading. The clock oscillator 22A generates, for example, a 32 MHz or 16 MHz clock as the clock CLK supplied to the CPU 11A. The clock CLK from the clock oscillator 22A is sent to the clock switching circuit 22A. The clock switching circuit 22A supplies a clock CLK or GND level output to the CP # 11A as the CPU 11A operation clock.

The bus controller 13 制御 controls the connection and disconnection between the CPU bus (local bus) 10 a and the system bus 10 b, as well as the reset signal RESET and the interrupt signal I for the CPU 11 A. Controls supply of NT, supply of clock CLK, and supply of power to CPU 11A.

Normally, the bus controller 13A turns on the switch circuit 12A to operate the CPU 11A, supplies the power supply voltage Vcc to the CPU 11A, and controls the clock. Controls the switching circuit 22A and supplies the clock CLK to the CPU 11A. However, when the CPU 11A is set to the sleep mode, the bus controller 13A stops supplying the clock CLK and also stops supplying the power supply voltage Vcc. When the supply of the clock CLK and the power supply voltage Vcc is stopped in this way, the bus controller 13A activates the reset signal RESET prior to the stop, and thereby the CPU 11 Reset A. The reason for stopping the supply of the clock CLK and the power supply voltage Vcc after resetting the CPU 11A in this way is that the supply of the clock CLK This is to prevent the CPU 11A from malfunctioning due to a clock phase shift due to stoppage or power cutoff.

Further, when the supply of the clock CLK and the power supply voltage Vcc is stopped in this way, the bus controller 1.3A disconnects the CPU bus 10a from the system bus 10Ob, and As a result, it is possible to prevent unnecessary current from flowing into the CPU 11A from various peripheral circuits connected to the system bus 1Ob.

The bus controller 13A indicates that the CPU 11A is ready for transition to sleep mode, and the bus status signals MZ I0, DZC, W / R from the CPU 11A. Recognize by 0

That is, when it becomes possible to shift to the sleep mode, as described above, the CPU 11A executes the Ha1t instruction, sets the signal MZIO to the level, sets the signal D / C to the “L” level, and sets the signal WZR to the level. To the level. Therefore, by detecting the levels of these signals, the bus controller 13A can recognize that the CPU 11A is in a state in which it can enter the sleep mode.

The bus controller 13A sends a hardware interrupt from the interrupt controller (PIC) 24A during the sleep mode (the supply of clock CLK and the power supply voltage Vcc is stopped). Upon receiving the requested IRQ, restart the supply of power supply voltage Vcc and clock CLK to return CPU 11A from sleep mode to normal operation mode. Next, the reset signal RESET is changed from active to inactive. Thereafter, the bus controller 13A supplies an interrupt signal INT to the CPU 11A.

The R0M14A stores a BIOS (Basic Input Output System) program such as a function subroutine waiting for key input. The dynamic RAM (DRAM) 15A is for storing an application program executed by the CPU 11A and the like, and at the time of transition to the sleep mode, the dynamic RAM (DRAM) 15A is used. (DRAM) 15 A saves the contents of the CPU 11 A register.

The real-time clock (RTC) 16 A is a module for realizing a clock function and a power render function. Its power is stored in its memory so that its memory contents will not be lost even when the power is turned off. 7 A is always supplied. The memory of the real time clock (RTC) 16 A stores the sleep mode identification flag described above.

This sleep mode identification flag is used to identify whether or not to return from the sleep mode. That is, when the reset signal RESET transitions to the active state or the active state, the CPU 11A executes the initialization of the internal state. In this case, it is not necessary to restore the saved register contents just by performing the bootstrap processing at the time of normal power-on, but when returning from the sleep mode, the register contents are restored to the CPU 11A. There is a need. As a result, the CPU 11A sets the reset signal RESET to the active state. When operation is resumed by transitioning from active state to reactive state, the real-time clock (RTC)

Check the sleep mode identification flag of 16 A to judge whether or not it is the return from sleep mode. Also, the real-time clock (RTC) 16 A periodically generates a timer interrupt request IRQ8 at a period of, for example, 500 ms. This timer interrupt request IRQ8 is supplied to the interrupt controller (PIC) 24A.

The keyboard controller (KBC) 17 A activates a key input interrupt request IRQ 1 to CPU 11 A when a key is input from a keyboard (not shown). This key input interrupt request IRQ1 is supplied to an interrupt controller (PIC) 24A.

The system timer 25A is a timer that periodically generates a timer interrupt request IRQ0 at a period of, for example, 55 ms. This timer interrupt request IRQ0 is supplied to the interrupt controller (PIC) 24A.

The interrupt controller (PIC) 24A supplies a hardware interrupt request IRQ to the bus controller 13A. That is, the interrupt controller (PIC) 24A generates a hardware interrupt request IRQ when it receives any of the timer interrupt request IRQ0, the key input interrupt request IRQ1, and the timer interrupt request IRQ8. , And supply it to the bus controller 13A. In this case, one of timer interrupt request IRQ 0 and timer interrupt request IRQ 8 It can be selectively masked by the interrupt mask register in the controller (PIC) 24A.

The power supply circuit 18A includes a DC-DC converter. This DC-to-DC converter receives the DC power supply voltage from the AC power adapter 19 A or the battery power supply 20 that converts AC commercial power to DC power, and converts it to the desired DC power supply voltage V Convert to cc.

FIG. 10 shows an example of a specific configuration of the bus controller 13A. As shown in the figure, the bus controller 13A has a power switching circuit 13A, a reset signal generating circuit 13A, an interrupt signal generating circuit 13A, an RS flip-flop. It is composed of a flop 135A and a bus gun Z separation circuit 135A.

The power supply switching circuit 1 3 1 A is for controlling the supply of the power supply Vcc to the CPU 11 A by controlling the switching circuit 12 A on and off, and the flip-flop 13 When 5A is reset, switch signal SW1 is set to "H" level to turn off switch circuit 12A. On the other hand, when the flip-flop 1335A is set, the power supply switching circuit 1331A sets the switch signal SW1 to "L" level and turns off the switch circuit 12A. In

The output of the flip-flop 135 A is supplied as a control signal SW 2 to the clock switching circuit 22 A. The clock switching circuit 22 A resets the flip-flop 13 5 A and stops the supply of the clock CLK to the CPU 11 A when it is switched off. Then, when flip-flop 135A is set, the supply of clock CLK is restarted.

The gate circuit 134A has the signals MZI ◦, DZC, and W / R set to “L” level, “L” level, and “H” level, respectively. Resets flip-flop 1 35 A when it recognizes that the instruction has been executed. The flip-flop 135A is set by an interrupt request IRQ from an interrupt controller (PIC) 24A.

The reset signal generator 1332A responds to the output "1" of the gate circuit 134A for resetting the flip-flop 1335A and resets the reset signal. Activate RESET. The reset signal generating circuit 132A sets the reset signal RSET to inactive in response to the interrupt request IRQ. The interrupt signal generating circuit 133A generates an interrupt signal I INT in response to the interrupt request I RQ.

The bus connection Z separation circuit 136 A is used to connect / separate the CPU bus 10 a and the system bus 10 b.When the power supply to the CPU 11 A is cut off, the peripheral circuit supplies power to the CPU 11 A. Separate the CPU bus 10a and the system bus 10b when the flip-flop 13 35 A is forced to prevent the flow. In this separated state, the CPU bus 10a is separated from the system node 10b, and the CPU bus 10a residing on the CPU 11A is fixed at the GND level. The prevention of wasteful current flow into the CPU 11 Significantly reduces current consumption of 11 A. In practice, it is preferable to fix not only the CPU bus 10a but also all signal lines connected to the CPU 11A to the GND level.

In the bus controller 13A configured as described above, the signals MZIO, DZC, and WZR are level,

When the “L” level and “H” level are detected, the reset signal RSET is set to an active state in response to the output “1” of the gate circuit 134. Further, when the flip-flop 135A is reset, a control signal SW2 for stopping the clock CLK is generated, and the power switch circuit 13A is used for the power switch circuit 12A. A control signal SW1 for turning off the switch is generated.

In this state, when an interrupt request (IRQ) is input, flip-flop 135A is set, and a control signal sW2 for restarting clock CLK supply is generated. Further, a control signal SW1 for turning on the power switch circuit 12A is generated from the power switch circuit 131A. Also, after a certain time (for example, 1 ms) has elapsed since the power switch circuit 12A was turned on, the reset signal RSET is set to inactive. Then, an interrupt signal INT is generated from the interrupt signal generating circuit 133A.

Next, with reference to FIGS. 11 to 13, a description will be given of a transition operation to the sleep mode and a return operation from the sleep mode in the portable computer shown in FIG.

First, referring to the flowchart in Fig. 11, The operation when switching to sleep mode to reduce the current consumption of 11 A is described.

When the CPU 11A enters the state of waiting for a key input during the execution of an application program, for example, the routine of a function waiting for an interrupt by BI0S as shown in FIG. 11 is usually used. Called by the show program. The function waiting for the interrupt is provided by the BIOS program.

In the interrupt-waiting function routine, the CPU 11A first determines whether or not a key input interrupt has occurred (step S11-1). This determination process is performed by the CPU 11A examining the cause of the interrupt when the interrupt signal INT is supplied to the CPU 11A. Whether or not the interrupt is caused by the key input interrupt request IRQ1 is determined, for example, by reading the status register of the interrupt controller 24A. When a key input interrupt occurs, the CPU 11A reads the key code from the keyboard controller (KBC) 117A (step S122-1), and then returns to the execution of the application program. .

On the other hand, if the key input interrupt has not occurred for a certain period of time, the CPU 11A recognizes that the sleep mode setting condition has been satisfied, and executes a subroutine for setting the sleep mode. Execute. Here, the CPU 11A first stores the register data at that time in the dynamic RAM (DRAM) 15A. (Step S 13-1). Next, the CPU 11A stores the sleep mode identification information of "1" in the real-time clock (RTC) 16A (step S14-1). Thereafter, the CPU 11A executes the Ha1t instruction for stopping the operation (step S15-1). This Ha It instruction prevents the CPU 11A from using the system bus 10.

When the CPU 11A executes the Ha1t instruction, the signal MZ I0, the signal DZC is set to "L", and the signal WZR are output to notify that the CPU 11A has stopped. To "H". Then, the state of Ha1t is maintained unless it is restarted.

The bus controller 13A monitors these signals (MZ IO, DWR CWR), and when it is found that the CPU 1A has executed the Ha1t instruction, the reset RESET signal Activate and reset CPU 1] A. Next, the supply of the clock CLK is stopped, and the supply of the power supply voltage Vcc is stopped. In addition, the bus controller 13A disconnects the CPU bus 1ϋa from the system bus 1Ob, fixes it to the GND level, and allows the current to flow from peripheral circuits to the CPU 11A. To prevent. In this way, CPU 11 A enters the sleep mode in which the supply of power supply voltage V cc is stopped.

Thereafter, the bus controller 13A resumes the supply of the power supply voltage Vcc to the CPU 11A in response to the hardware interrupt request IRQ from the interrupt controller 19, and then restarts the clock. Lock CLK supply is resumed, and after that, CPU bus 10a is Connect to system bus 1 ϋ b.

After a lapse of about 1 ms after the above processing is completed, the pass controller 13A causes the reset signal REST to transition from the active state to the inactive state.

When the reset signal RESET transitions to inactive, the CPU 11A starts operation, initializes internal registers, and fetches an instruction from a specific address. As a result, the routine shown in FIG. 12 is executed. The routine in FIG. 12 is the same routine that is executed when a reset switch for forcibly setting CPU 1] A to the initial state is turned on or when the power is turned on.

In the routine shown in FIG. 12, first, the CPU 11A checks the contents of the sleep mode identification flag stored in the real-time clock (RTC) 16A. (Step S21-1). If the sleep mode identification flag is "0", the CPU 1 does not return from sleep mode, but starts the system normally by turning on the system power or turning on the reset switch. 1A executes the bootstrap process (step S22—).

On the other hand, if the sleep mode identification flag is "1", the CPU is returning from sleep mode. Therefore, the CPU 11A uses the real-time clock (RTC) 16A. The sleep mode identification flag is rewritten to “0” (step S23-1), and the saved register contents are then transferred from dynamic RAM (DRAM) 15A. Load and restore register contents (Step S24-1) o Then, the CPU 11A returns to the state before the sleep mode was set, and executes a predetermined interrupt process corresponding to the interrupt signal INT.

As described above, the sleep mode function of this embodiment stops supply of the power supply voltage Vcc to the CPU 11A while the CPU 11A is reset, and stops the supply of the power supply Vcc. This reduces the current consumption of the CPU 11A.

FIG. 13 shows the operation timing of the sleep mode operation described above. As shown in the figure, when transitioning from the normal mode to the sleep mode, the CPU 11A executes the Halt instruction and then activates the reset RESET signal. With the 1 A reset, the clock CLK is stopped, and the supply of the power supply Vcc to the CPU 11 A is also stopped.

When returning from the sleep mode to the normal mode, after a hardware interrupt request (IRQ) is generated, first, the power supply voltage V cc to the CPU 11A is turned on. The clock CLK supply is restarted, and then the reset signal RESET is deactivated, thereby restarting the CPU 11A operation.

Note that during the supply stop period of the power supply voltage Vcc to CPϋ11A, the reset signal RESET may be temporarily set to inactive as shown by the dotted line. This is because, for example, the bus controller 13A responds to the execution of the Ha1t instruction by the CPU 11A, so that the bus controller 13A 4.1

This can be realized by outputting a reset pulse that maintains the state, and outputting a reset pulse that maintains the active state for a certain period in response to the hardware interrupt request IRQ.

Next, an example of another specific configuration of the bus controller 13A will be described with reference to FIG.

The bus controller 13A in Fig. 10 can power off the CPU 11A by the signals (M / I0, DZC, W / R) output by executing the Ha1t instruction. The bus controller 13A 'in Fig. 14 recognizes that the status has reached a state of な, and that the retraction of the register has been completed, based on the notification data issued from the CPU 11A. Thus, the CPU 11A recognizes that the power supply can be stopped.

That is, the controller 13A includes a decoder 201A and a register 202A instead of the gate circuit 134A. The decoder 201A decodes the address from the CPU 11A, and sets a predetermined 1-bit notification data on the bus 10b to the register 202A when the address has a predetermined value. To When the notification data is set in the register 202A, the reset signal RESET is activated by the reset signal generation circuit 132A, and thereafter, the flip-flop 135A is reset. As a result, the control signal SW1 for stopping the supply of the power supply voltage Vcc and the control signal SW2 for stopping the clock CLK are generated.

Using a bus controller 13A 'with such a configuration For example, even if the CPU 11A does not execute the Ha1t instruction, it is possible to recognize that the CPU 11A is in a power-stoppable state.

As described above, in the portable computer of the second embodiment, the supply of the power supply voltage Vcc to the CPU 11A is turned off while the CPU 11A is reset. Therefore, it is possible to prevent a situation in which the CPU 11A malfunctions due to the stop of the power supply. Also, since the power supply voltage V cc of CPU 11A is turned off instead of lowering the frequency of the clock CLK as in the normal sleep mode, power consumption can be significantly reduced.

Et al is, when the re-set the CPU 1 1 A is evacuated the register contents of the CPU 1 1 A, the the saved registers evening content, power supply V c _c is resumed, re-Se Tsu It returns when the reset signal RESET is set to inactive. Therefore, the operation of the CPU 11A can be started from the state before the stop of the clock CLK, and the normal operation of the CPU 11A can be reliably ensured.

Such a CPU power control system is particularly suitable for implementing the sleep mode function of a CPU with an internal oscillator, but operates in synchronization with an external clock without an internal oscillator including a PLL circuit. Of course, even if it is applied to the CP する, the power consumption can be reduced without causing a malfunction.

In the second embodiment, whether the CPU 11Α has returned from the sleep mode or the system has been turned on. The sleep mode identification flag is set by software in the CPU 11A in order to identify whether or not the device is in the sleep mode. For example, a flip flop or the like is provided in the bus controller 13A. It is also possible to set the sleep mode identification flag on the flip-flop in a hardware manner.

Further, in the second embodiment, the sleep mode in which not only the power supply voltage Vcc of the CPU 11A is turned off, but also the supply of the clock CLK is stopped, but only the power supply Vcc is turned off. You may.

In order to maintain the sleep mode for a long time, it is preferable that the system timer interrupt request IRQ0 during the sleep mode is masked by the interrupt controller 24A. By doing so, the system timer interrupt request IRQ0 generated in units of 55 ms is prohibited. For this reason, the sleep mode period can be set to 55 ms or more, and the power consumption can be further reduced.

In this case, the processing of CPU 11 A when shifting from the normal mode to the sleep mode is performed as shown in FIG.

That is, in this case, the steps S 13-1 to S 15 11 of the subroutine for transition to the sleep mode shown in FIG. 1 — 1 is added. In step S100-1, the CPU 11A sets the timer interrupt cycle of the real time clock (RTC) 16A to 500 ms. This means that the data indicating 500 ms is transferred to the real-time clock (RTC) 16 A This is realized by writing to a predetermined register within the register. In step S101-1, CPU 11A disables the timer interrupt for system timer 25A and disables the timer interrupt for real-time clock (RTC) 15A. . This is achieved by writing predetermined mask data to the interrupt mask register of the interrupt controller (PIC) 24A.

As a result, in sleep mode, the system timer interrupt request IRQ 0 generated in units of 55 ms is prohibited, and the real-time clock (RTC) 16 A timer interrupt request I generated in units of 500 ms is disabled. RQ 8 is allowed. For this reason, the sleep mode setting period can be set to 55 ms or more, and power consumption can be further reduced.

Here, the reason why the timer interrupt cycle of the real-time clock (RTC) 16 A was set to 500 ms is to suppress the clock function of the application program. In other words, when an abbreviated program that has the function of digitally displaying the time on the display screen is being executed, it is necessary to update the timer count at least within 1 s. You. For this reason, the maximum setting period of the sleep mode is limited to 500 ms by using a timer interrupt in units of 500 ms.

Also, when the system timer interrupt request IRQ0 is disabled and the mode shifts to the sleep mode, the CPU 11A performs a process for shifting the mode from the normal mode to the sleep mode. The process is performed as shown in Figure 16.

That is, in this case, in addition to the steps S23-1 and S24-] shown in FIG. 16, step S102-1 is executed. In step S102-1, CPU 11A enables the system timer 25A timer interrupt and disables the real-time clock (RTC) 16A timer interrupt. Bull. This is realized by writing predetermined mask data to an interrupt mask register of an interrupt controller (PIC) 24A. As a result, in the normal mode, the timer interrupt in units of 55 ms is effectively enabled.

Hereinafter, a third embodiment will be described.

FIG. 7 shows a system configuration of a portable computer according to a third embodiment of the present invention. This portable computer uses two delay circuits to generate the reset-to-active reset signal transition timing and the reset signal. It is configured so that the timing of switching the clock CLK frequency after setting it as active can be optimally controlled.

This portable computer is a computer driven by an AC commercial power supply or a battery detachably attached to the computer main body, and includes a CPU 11B, a reset generation circuit 12B, and a computer. Lock switching circuit 13 B, timing control circuit 14 B, clock oscillator 15 B, frequency divider circuit 16 B, trigger circuit 17 B, latch circuit] 8 B, Dynamic RAM (DRAM) 19 B, Programmable Interrupt Controller (PIC) 20 B, Keyboard Controller (KBC) 21 B, System Timer 22 B, and Ryanore Time Clock (RTC) 23 B I have.

The CPU 11B is responsible for controlling the entire system. The components, that is, the timing control circuit 14B, the DRAM 19B, and the interrupt controller 20 via the system bus 10B. B, connected to the keyboard controller (KBC) 21B, system timer 22B, and real-time clock (RTC) 23B. The CPU 11 B is composed of, for example, the above-mentioned microphone port processor 80486, and has an internal oscillator 11 B including a PLL circuit. In other words, the CPU 1] B internally generates a clock several times the clock CLK supplied through the clock switching circuit 13B by the internal oscillator 111B, and uses the generated clock. This is a configuration that operates at high speed.

The CPUIB determines whether sleep mode setting conditions have been established by executing a BIOS (Basic Input Output System) program that is controlled by the running application program. When the condition is satisfied, the data of each register in the CPU 1 IB is saved, and the Ha1t instruction is executed sequentially. The sleep mode setting condition is satisfied, for example, when the operator does not perform a key input operation for a fixed period or more. The contents of the CPU 11B register are saved to DRAM 19B. When the CPU 11B executes the Ha1t instruction to stop the execution of the program and the bus access, the CPU 11B determines that the CPU 11B has been set to the stop state. Notify 14 B.

The reset generation circuit 12B is for supplying the reset signal RESET to the CPU 11B. The reset generation circuit 12B outputs the reset signal RESET under the control of the timing control circuit 14B. Set to active or inactive. When the reset signal RSET is activated, CPU11B is reset and all operations of CPU11B are stopped. When the reset signal RSET transitions from active to inactive, CPU11B resumes operation.

The clock switching circuit 13B selects one of the high-speed clock CLK1 having a higher frequency and the lower-speed clock CLK2 having a lower frequency, and selects the clock CLK1. And supply it to CPU 11B. This clock switching circuit 13B normally selects the high-speed clock CLK1 to operate the CPU 11B at high speed, but sets the CPU 11B to sleep mode. In some cases, the clock CLK is switched from the high-speed clock CLK1 to the low-speed clock CLK2 under the control of the timing control circuit 14B. The frequency of the low-speed clock CLK2 is, for example, 1 Z2 of the high-speed clock CLK1.

The high-speed clock CLK1 is generated by the clock oscillator 15B, and the low-speed clock CLK2 is obtained by dividing the high-speed clock CLK1 by the frequency divider 1 6 Divided by B Therefore, it is obtained.

The timing control circuit 14B controls the operation timing of the reset generation circuit 12B and the clock switching circuit 13B. That is, when the CPU 11B is set to the sleep mode, the evening control circuit 14B outputs the clock CLK after the CPU 11B is reset by the reset signal RESET being activated. The reset generation circuit 12B and the clock switching circuit 13B are controlled so that the high-speed clock CLK1 switches to the low-speed clock CLK2. When returning the CPU 11B from the sleep mode, the timing control circuit 14B resets the reset signal RESET after the clock CLK is switched from the low-speed clock CLK2 to the high-speed clock CLK1. The clock switching circuit 13B and the reset generation circuit 12B are controlled so that the CPU 11B restarts when the CPU transitions from active to inactive.

As shown, the timing control circuit 14B includes a register 141B and two delay circuits 142B and 143B. In the register 141B, notification data indicating the stop state issued from the CPU 11B is set. When this notification data is set, a reset 0 N signal for activating the reset signal RESET is sent to the reset generation circuit 12B, and thereafter, a predetermined time is set by the delay circuit 143B. At a delayed timing, the switch signal SW1 for switching the clock CLK to the low-speed clock CLK2 is used as the clock switching circuit. Sent to 1 3 B. When a trigger signal is input from the trigger circuit 17B, a switch signal SW2 for returning the clock CLK from the low-speed clock CLK2 to the high-speed clock CLK1 is generated. Sent to the clock switching circuit 13B, and then reset by the delay circuit 142B to make the reset RESET signal inactive at a certain time.

0 F 'F signal is sent to reset generation circuit 12B.

When a hardware interrupt signal INT is issued from the interrupt controller (PIT) 2〇B, the trigger circuit 17B outputs a trigger signal in response to the interrupt signal INT. The interrupt signal INT from the interrupt controller (PIT) 2 OB is also sent to the latch circuit 18B. The latch circuit 18B is a transparent-type latch circuit, which outputs the interrupt signal output from the interrupt controller (PIT) 20B as it is, and then outputs the interrupt signal for a certain period of time. Interrupt signal

Hold 1 N T.

The DRAM 19B is for storing an application program executed by the CPU 11B, and is stored in the DRAM 19B at the time of transition to the sleep mode. Saves the contents of the CPU 11B register.

The interrupt controller (PIT) 20B is a key input interrupt request IRQ1 from the keyboard controller (KBC) 21B, a timer interrupt request IRQ0 from the system timer 22B, a real-time clock ( RT C) 23 B Outputs the wear interrupt signal INT.

When there is a key input from a keyboard (not shown), the keyboard controller (KBC) 21 B generates a key input interrupt request IRQ1 to notify the CPU 11 B of the key input interrupt. The key input interrupt request IRQ1 is supplied to the interrupt controller (PIT) 20B.

The stem timer 22B is a timer that periodically generates a timer interrupt request IRQ0 at a cycle of, for example, 55 ms. This timer interrupt request IRQ0 is supplied to the interrupt controller 20B.

The real-time clock (RTC) 23B is a module that implements the clock function and force rendering function. Its internal memory has a backup power supply VBK Is always supplied. Also, the memory of the real-time clock (RTC) 23B stores a sleep mode identification flag. The sleep mode identification flag can be used to identify whether the CPU 11B has returned from the sleep mode to the normal mode or has been powered on by the system. That is, the transition from the active state of the reset signal RESET to the active state is performed not only when the CPU 11B returns from the sleep mode to the normal mode but also when the system power is turned on. It also occurs at the time. When the power is turned on, it is not necessary to restore the saved register contents just by performing normal bootstrap processing, but when returning from sleep mode, the contents of the registers are restored. It is necessary to return the contents to CPU 11B. Therefore, when the reset signal RESET changes from the active state card to the inactive state, the CPU 11B checks the sleep mode identification flag of the real-time clock (RTC) 23B, Thus, it is determined whether or not a return from the sleep mode has been made.

The real-time clock (RTC) 23B generates a timer interrupt request IRQ8 periodically at a cycle of, for example, 500 ms. This timer interrupt request IRQ8 is supplied to the interrupt controller 20B.

FIG. 18 shows the operation timing of the timing control circuit 14B when the CPU 11B is set to the sleep mode.

As shown, when the CPU 11B shifts from the normal mode to the sleep mode, first, a reset 0N signal is generated, whereby the reset signal RESET becomes active. As a result, the CPU 11B is set to the reset state. At this time, the clock CLK is still the high-speed clock CLK1. The CPU 11B stops all operations while the reset signal RESET is active. Next, after the delay time of the delay circuit 143B has elapsed, the switch signal SW1 is generated, whereby the clock CLK of the CPU 11B is changed to the high-speed clock CLK1 and the low-speed clock. Switch to CLK2. During the period when the low-speed clock CLK2 is sent to the CPU 11B, the current consumption of the CPU 11B is minimized. Have been.

Thereafter, when a trigger signal is input due to the occurrence of a hardware interrupt, the switch signal SW2 is output, whereby the clock CLK of the CPU 11B is changed from the low-speed clock CLK2 to the high-speed clock CLK2. Switch to clock CLK1.

Next, after a lapse of the delay time of the delay circuit 142B, a reset 0 FF signal is generated, whereby the reset signal RESET becomes inactive. As a result, CPU 11 B resumes operation. The time from when the clock CLK is switched from the low-speed clock CLK2 to the high-speed clock CLK2 until the reset signal RESET transitions from active to inactive follows the specifications of the CPU 11B. Must be specified exactly. If the time is too short, the CPU 11B malfunctions. If the time is too long, the operation start timing of the CPU 11B is delayed, thereby deteriorating the operation performance of the system.

In the third embodiment, the time from when the clock CLK is switched from the low-speed clock CLK2 to the high-speed clock CLK2 to when the reset signal RESET transitions from active to inactive is: It is controlled appropriately by hardware by the delay circuit 142B. Therefore, the operation start timing of CPU 11 B can be advanced within a range that does not cause a malfunction of CPU 11 B.

Next, referring to the flowcharts of FIGS. 19 to 21, the sleep mode in the portable computer of the third embodiment will be described. The transition operation to the sleep mode and the return operation from the sleep mode will be described.

The flowchart in FIG. 19 shows the operation of the CPU 11B when shifting to the sleep mode, and the flowchart in FIG. 20 shows the CPU 11B when returning from the sleep mode. The operation of B is shown. The flowchart of FIG. 21 shows the flow of the entire processing including the operation of the timing control circuit 14B.

First, the operation of the CPU 11B when transitioning to the sleep mode will be described with reference to the flowchart in FIG.

When the CPU 11B waits for a key input during execution of an application program, for example, normally, an interrupt waiting function routine as shown in FIG. 19 is called by the application program. Is done. This interrupt waiting function is provided by the BIOS program.

In the interrupt waiting function routine, first, the CPU 11B determines whether or not a key input interrupt has occurred (step S11-2). This determination process is performed by the CPU 11B examining the cause of the interrupt when the interrupt signal INT is supplied to the CPU 11B. Whether or not the interrupt is caused by the key input interrupt request IRQ1 is determined, for example, by reading the status register of the interrupt controller 20B. When a key input interrupt occurs, CPU 11 B La (KBC) Reads the 2 1 B key code (step S 12-2), and then starts executing the application program.

On the other hand, if no key input interrupt has occurred, the CPU 11B recognizes that the sleep mode setting conditions have been satisfied, and executes a subroutine for setting the sleep mode. Here, the CPU 11B first stores the contents of the register at that time in the dynamic RAM (DRAM) 19B (step S13-2). Next, the CPU 11B stores the sleep mode identification flag of "1" in the memory of the real-time clock (RTC) 23B (step S14-2). Thereafter, the CPU 11B executes the Ha1t instruction (HLT) for stopping the operation (step S15-2). This Ha1t instruction prevents CPU11B from using system bus 10B.

When the CPU 11B executes the Ha It instruction, the notification data is sent to the register 14 1B of the timing control circuit 14B in order to notify that the CPU 11 B has stopped. Light You O oo

Timing control circuit] 4B controls the reset generation circuit 12B in response to the setting of the notification data to the register 141B as shown in FIG. The reset signal RESET [Step S21-2]. As a result, the CPU 11B is set to the reset state, and all operations of the CPU 11B are stopped. Next, when the delay time of the delay circuit 143B elapses, the timing control circuit 14B controls the clock switching circuit 13B to change the clock CLK to the high-speed clock CLK. Switch from 1 to low-speed clock CLK 2 (step S22-2). As a result, the CPU 11B enters the sleep mode driven by the low-speed clock CLK2.

After this, when the interrupt controller 20B power is generated and the hardware interrupt signal INT is generated (step S23-2), the trigger signal is output to the timing control circuit 14B. Is input to Upon receiving the trigger signal, the timing control circuit 14B controls the clock switching circuit 13B to reduce the clock CLK to the low-speed clock CLK2 and the high-speed clock. Switch to lock CLK1 (step S24-2). Thereafter, when a delay time (for example, 1 ms) by the delay circuit 14 2 B has elapsed, the timing control circuit 14 B inactivates the reset signal RESET to restart the CPU 11 B. To

When the reset signal RESET (inactive), CPU] 1B starts operation, initializes internal registers, and executes instructions from a specific address. Thus, the routine of FIG. 20 is executed. The routine in FIG. 20 is the same routine that is executed when a reset switch for forcibly setting CPU11B to the initial state is turned on or when the power is turned on.

In the routine shown in Fig. 20, first, the CPU 11B is stored in the memory of the real-time clock (RTC) 23B. The content of the sleep mode identification flag is checked (step S31-2). If the sleep mode identification flag is “0”, CP ϋ 11 B is not booted because it is not a return from sleep mode but a normal system startup by turning on the power or turning on the reset switch. Execute the trap processing (step S32-2). In this bootstrapping process, peripheral circuit initialization, operating system startup, and the like are performed.

On the other hand, if the sleep mode identification flag is “1”, the CPU 11Β is in sleep mode of the real-time clock (RTC) 23Β because it is a return from sleep mode. Rewrite the identification flag to "0" (step S33-2), and then load the saved register contents from the dynamic RAM (DRAM) 19B to the internal registers and restore the register contents (step S33-2). Step S34—2). Then, the CPU 11B receives the interrupt signal INT output from the latch circuit 18B and executes a predetermined interrupt process.

As described above, the sleep mode function of the third embodiment switches from the high-speed clock CLK 1 to the low-speed clock CLK 2 while the CP-1 IB is reset, and this low-speed clock CLK By supplying 2 as the clock CLK to the CPU 11B, the current consumption of the CPU 11B is reduced.

Next, an example of another specific configuration of the timing control circuit 14B will be described with reference to FIG.

The timing control circuit 14B 'in FIG. It has three operation modes for controlling the operation of the generator circuit 12B and the clock switching circuit 13B. The first mode is a mode for automatically setting the CPU 11B to the sleep mode as described above. The second mode is a mode for switching and using the CPU 11B from the high-speed operation to the low-speed operation when a switching request is received from the operator. The third mode is a mode in which the CPU 11B is returned from the low-speed operation to the high-speed operation when a switching request is also received from the operator. The switching request from the operator is notified to the CPU 11B by, for example, a predetermined keyboard operation by the operator in a setup process or a pop-up process, or an operation of a dip switch of the computer main body.

The timing control circuit 14 B ′ is composed of a register 201 B, a register 202 B, a timing control circuit 203 B of 笫 1, and a second timing control circuit 204 B. And a third timing control circuit 205B, and a reset timer 206. In the register 20] B, notification data indicating that the CPU 1] B has been set to the stop state is set. Data for designating one of the operation modes of the timing control circuit 14B 'is set in the register 2◦2B. The first timing control circuit 203B is for performing timing control in the first mode, and shifts to the sleep mode and returns from the sleep mode. Used for The second timing control circuit 204B is for performing timing control in the second mode, and switches the CPU 11B from high-speed operation to low-speed operation. Used when changing. The third timing control circuit 205B is used when switching CPϋ11B from low-speed operation to high-speed operation. The reset timer 206 defines a period during which the reset signal RES Ε is kept active in the second or third mode.

When the first mode (sleep mode) is specified, CPU1ϊB sets data D1 to register 202B. When the second mode (switching from high speed to low speed) is specified, CPU 1] B sets data D2 to register 202B. Further, when the third mode (switching from the low speed to the high speed) is specified, the CPU sets the data D3 in the register 202B. When data D1 is set, the first timing control circuit 203B is set in an operable state, and similarly, when data D2 is set, the second timing control circuit 203B is set. When the data D 3 is set, the third timing control circuit 205B is set to an operable state.

Of these three timing control circuits 203 B, 204 B, and 205 B, the timing control circuit that is set to be in an operable state is set to register 201 B by CPU 11 B. The operation starts when data indicating that the operation of the CPU 11B is stopped is set in the CPU.

The first timing control circuit 203B has a configuration including first and second two delay circuits similarly to the timing control circuit 14B described with reference to FIG. Mining is also time This is the same as the switching control circuit 14B. That is, when the data indicating that the operation of the CPU 11B is stopped is set in the register 201B, the first evening im- aging control circuit 203B first responds to the signal S1. Controls the reset generation circuit 12B and activates the reset signal RESET. Next, the first timing control circuit 203B is controlled by the signal T1 when the reset signal RESET has been activated and the delay time of the first delay circuit has elapsed. Controls the switching circuit 13B to switch the clock CLK from the high-speed clock CLK1 to the low-speed clock CLK2.

Then, upon receiving the trigger signal, the first timing control circuit 203B controls the clock switching circuit 13 # by the symbol T1, and Switch the clock CLK from the low-speed clock CLK2 to the high-speed clock CL # 1. Next, when the first timing control circuit 203 3 has switched by the clock and the delay time of the second delay circuit has elapsed, the reset signal RES Ε によって by the signal S1. Make inactive.

Next, the operation of the second timing control circuit 204 # will be described with reference to FIG.

When the operator designates the second mode by operating a dip switch or performing a keyboard operation in a setup process or a pop-up process, the CPU 11 1 stores the data D2 in the register 2 22. At the same time, save the register and execute the Ha1t instruction, and then set the register 201B to the data indicating the stop state. As a result, the second timing control circuit Road 2 [) 4 B is activated.

As shown in the timing chart of FIG. 23, the second timing control circuit 204B first controls the reset generation circuit 12B by the signal S2. The reset signal RESET is activated, and then the clock switching circuit 13B is controlled by the signal T2 to switch the clock CLK from the high-speed clock CL'K1 to the low-speed clock CLK2. Then, after a lapse of a predetermined period defined by the reset timer 206B, the reset signal RSET is made inactive.

When the reset signal RESET transitions to inactive, the CPU 11B returns to the original operating state by restoring the saved register, and operates at a low speed by the clock CLK2. Next, the operation of the second timing control circuit 204B will be described with reference to FIG.

When the operator specifies the third mode by operating a dip switch or performing a keyboard operation in a setup process or a pop-up process, the CPU 11B sets the data D3 to the register 202B, Save the register in CPU 11B, execute the Ha1t instruction, and then set the data indicating the stop state in register 20IB. Thus, the third evening imaging control circuit 205B is activated.

The second timing control circuit 205B first controls the reset generation circuit 12B by the signal S2 as shown in the evening chart of FIG. To activate the reset signal RESET, and then clock it with signal T2. The switching circuit 13B is controlled to switch the clock CLK from the low-speed clock CLK2 to the high-speed clock CLK]. Then, after a lapse of a predetermined period defined by the reset timer 206 #, the reset signal RES ## is made inactive.

When the reset signal RES Τ changes to inactive, the CPU 11 を returns to the original operating state by restoring the saved register, and operates at high speed with the clock CLK 1. . As described above, in the portable computer of the third embodiment, the two clock powers of the high-speed clock CLK1 and the low-speed clock CLK2 are used for the CPU 1 IB. Selectively used as clock CLK.

In this case, the switching of clock CLK is performed in the reset state of CPU] 1B <CPU 1B, so that the operation of CPU 11B is discontinuous in the clock phase at the time of clock switching. Is not affected at all. When the CPU 11B is reset, the register contents of that CPU 1] are saved. The saved register contents are restored when clock switching is completed and reset signal power is set to inactive. In this case, the period from when the clock is switched to when the reset signal transitions from active to inactive is appropriately defined by means of the delay circuit. Therefore, it is possible to prevent the CPU 11B from malfunctioning due to the period in which the reset signal is actively maintained after the clock is switched, and to prevent the period from being too long. It is possible to prevent a decrease in operating performance due to the above. Note that such a clock switching system is particularly suitable for realizing the sleep mode function of a CPU having an internal oscillator.For a CPU that does not have an internal oscillator and operates in synchronization with an external clock, Even if it is applied, it is needless to say that the power consumption can be reduced without causing a malfunction.

Also, here, switching between two clocks, the high-speed clock CLK1 and the low-speed clock CL'K2, has been described, but three or more clocks with different operation speeds are used. You can also use clocks to switch the operating clock between them. In this case, the power consumption can be reduced by lowering the clock frequency, and it is preferable to use the slowest clock in sleep mode. In the sleep mode, the supply of the clock to the CPU 11B may be stopped by supplying a GND level DC signal to the CPU 11B as in the first embodiment. By doing so, the current consumption can be further reduced.

Furthermore, in order to maintain the sleep mode for a long time, the system timer interrupt request IRQ0 during the sleep mode is preferably masked by the interrupt controller 20B. In this way, the system timer interrupt request IRQ0 generated in units of 55 ms is prohibited. For this reason, the sleep mode period can be set to 55 ms or more, and the power consumption can be further reduced.

In this case, the processing of CPU 11 B when shifting from the normal mode to the sleep mode is performed as shown in FIG. .

In other words, in this case, the sleep mode shown in Fig. 19 Steps S100-3 and S101-2 are added to the subroutine steps S13-2 to S15-12 of the subroutine for transferring the code. In step S100-2, the CPU 11B sets the timer interrupt cycle of the real-time clock (RTC) 23B to 500 ms. This is realized by writing data indicating 500 ms to a predetermined register inside the real-time clock (RTC) 23B. In step S101--2, the CPU 11B disables the timer interrupt of the system timer 22B and disables the timer interrupt of the real-time clock (RTC) 23B. . This is achieved by writing predetermined mask data to the interrupt mask register of the interrupt controller (PIC) 20B.

As a result, in sleep mode, the system timer interrupt request IRQ 0 generated in units of 55 ms is disabled, and the real-time clock (RTC) 23 B generated in units of 500 ms is disabled. Timer interrupt request IRQ 8 is enabled. For this reason, the set period of the sleep mode can be set to 55 ms or more, and the power consumption can be further reduced.

The reason why the timer interrupt cycle of the real-time clock (RTC) 23B was set to 500 ms is to support the clock function of the application program. In other words, if you are running an absorption program that has the function of digitally displaying the time on the display screen, it is possible to update the timer count within at least] seconds. Needed. For this reason, the maximum setting period of the sleep mode is limited to 500 ms by using a timer interrupt in units of 500 ms.

Also, when the system timer interrupt request IRQ0 is disabled and the system shifts to the sleep mode, the processing of the CPU 11B for shifting from the normal mode to the sleep mode is performed. Ho, 笫 is performed as shown in Figure 26.

That is, in this case, in addition to steps S23-2 and S24-2 shown in FIG. 20, step S102-2 is executed. In step S102-2, the CPU 11B enables the timer interrupt of the system timer 22B, and disables the timer interrupt of the real time clock (RTC) 23B. This is achieved by writing predetermined mask data to the interrupt mask register of the interrupt controller (PIC) 20B. This enables timer interrupts in 55 ms units in normal mode.

Hereinafter, a fourth embodiment of the present invention will be described.

FIG. 27 shows a system configuration of a portable computer according to the fourth embodiment of the present invention. This portable computer is configured so that the number of clock cycles of the CPU can be smoothly changed by using a voltage controlled oscillator (VCO). In other words, this portable computer has a system bus 10C, CPU 11C, voltage switching circuit 12C, voltage controlled oscillator (VCO) 13C, Sim clock (RTC) 14 C, keyboard controller

It has (KBC) 15C, system timer 16C, programmable interrupt controller (PIC) 17C, and dynamic RAM (DRAM) 18C.

The CPU 11C is responsible for controlling the entire system of the portable computer, and includes a voltage switching circuit 12C and a real-time clock via a system bus 10C.

(RTC) 14C, keyboard controller (KBC) 15Cs system timer 16C, interrupt controller

(PIC) 17 C and dynamic RAM (DRAM) 18 C.

The CPU 11C is composed of, for example, a microprocessor 80486, and has an internal oscillator 11C including a PLL circuit to generate and operate a high-speed clock internally. That is, this CPU 11C is a voltage controlled oscillator

(VC0) 13C The internal clock generated by the internal oscillator 1] 1C is several times the clock CLK supplied by the internal clock, and it is used to operate at high speed. is there.

The CPU 11C issues a clock CLK switching request to the voltage switching circuit 12C. This clock switching request is issued, for example, when the CPU 11C shifts from the normal mode operating in the high-speed clock to the sleep mode operating in the low-speed clock, or in the sleep mode. Issued when returning to normal mode from

That is, the CPU 11C executes the running application By executing the BIOS (Basic Input 0 ut pu ί Sys ieoi) program called by the program, it is determined whether or not the sleep mode setting conditions have been established. Instruct the voltage switching circuit 12C to switch the clock. The sleep mode setting condition is satisfied when the CPU 11C is in a waiting state, for example, when a key input operation is not performed by an operator for a fixed period or more. Also, if the hardware interrupt signal INT is input from the interrupt controller 17C during the sleep mode operating at the low-speed clock, the CPU 11C returns from the sleep mode. For this purpose, the voltage switching circuit 12C is instructed to switch the low-speed cook to the high-speed cook.

The clock switching instruction is issued not only when executing the sleep mode function as described above, but also when, for example, using application software configured to operate at a low speed. . In this case, a clock switching request is notified to the CP 1 11C by an operator's key input operation or the like, and a clock switching instruction is issued from the CPU 11C to the voltage switching circuit 12C accordingly. You.

The voltage switching circuit 12C changes the control voltage supplied to the voltage controlled oscillator (VC0) 13C according to the clock switching instruction from the CPU 11C. In this case, the voltage switching circuit 12C gradually raises or lowers the control voltage so that the oscillation frequency of the voltage-controlled oscillator (VC0) 13C changes continuously. Regarding the specific configuration of this voltage switching circuit 12C, This will be described later with reference to FIGS. 30 to 32.

The voltage controlled oscillator (VCO) 13 C has a configuration in which the oscillation frequency is variably set according to the value of the control voltage from the voltage switching circuit 12 C, and the oscillation output is clocked to the CPU 11 C. Supplied as CLK.

FIG. 28 shows a change characteristic of the cycle of the clock CLK with respect to the control voltage generated from the voltage switching circuit 12C. In this example, it is assumed that the voltage-controlled oscillator (V C0) 13 C is configured so that the oscillation frequency becomes lower as the control voltage becomes higher.

When the clock CLK of CPU11C is switched to the high-speed clock force or the low-speed knob, the control voltage is initially stable at a certain low voltage value V1 (period A). In this period A, the voltage-controlled oscillator (V C0) 13 C is generating a high-speed clock C LK.

In this state, when the control voltage is gradually increased, the frequency of the clock CLK is gradually reduced and the period of the clock CLK is gradually increased. Go (period B). Finally, when the control voltage is stabilized at a certain high voltage V 2, the clock CLK output from the voltage-controlled oscillator (VC 0) 13 is also stabilized at a low frequency, 11 C is supplied with low-speed intake (period C).

What is important here is that the frequency and phase of the clock CLK are continuously changing during the period (B). This means that the frequency of the clock CLK switches rapidly. Instead, it is smoothly and continuously changed from a high frequency to, for example, a half of the low frequency.

Also, when switching the clock CLK of the CPU 11C from the low-speed clock to the high-speed clock, the frequency and phase of the clock CLK are smoothly and continuously as shown in Fig. 29. Be changed.

FIG. 30 shows a first specific example of the voltage switching circuit 12C.

This voltage switching circuit 12 C-1 is configured to change the control voltage using a DZA converter, and is composed of a register 121 C and a DZA converter 122 C as shown in the figure. It has been. The clock frequency instruction data issued from the CPU 11C is stored in the register 121C. The DZA converter 122C converts the value of the instruction data stored in the register 121C from a digital value to an analog value. For example, if the instruction data is a data D1 indicating a high-speed cut-off, the D / A converter 122C generates an analog voltage V1 corresponding to the data D1. . If the instruction data is data D2 indicating the low-speed clock (here, D1> D2), the DZA converter 122C outputs the analog voltage V corresponding to the data D2. Generate 2

Data of register 121C << When the CPU 11C updates D1 to D2, the analog voltage output from the DA converter 122C gradually changes from voltage V1 to voltage V2 Is performed. Also, data in register 1 2 1 C is updated from D 2 to D 1 In this case, the analog voltage output from the DZA converter 122C is gradually changed from the voltage V2 to the voltage V1.

FIG. 31 shows a second specific example of the voltage switching circuit 12.

The voltage switching circuit 12C-2 has a configuration in which the control voltage is changed by using an integration circuit having a relatively large time constant. As shown in the figure, the decoder 123C and the D flip-flop are used. It is composed of a loop 124 C and an integration circuit 125 C.

In the voltage switching circuit 12C-2, the address on the bus 10C is decoded by the decoder 123C, and when the address has a predetermined value, the predetermined 1-bit data on the bus 10C is decoded. Is latched to D flip flop 124 C. The 1-bit data specifies the frequency of the clock CLK. Data "0" indicates a high-speed clock and data "1" indicates a low-speed clock. When the latch data of D flip-flop 124C is changed from data "0" to data "1", D flip-flop 124C generates a level Q output. In this case, the control voltage of the voltage controlled oscillator (VC 0) 13 C is gradually increased from the voltage VI to the voltage V 2 by the time constant of the integrating circuit 125 C. When the latch data of D flip-flop 124 C is changed from data “1” to data “0”, the control voltage of voltage-controlled oscillator (VC 0) 13 C is applied to the integration circuit 1 With a time constant of 25 C, the voltage is gradually reduced from voltage V2 to voltage V1. FIG. 32 shows a third specific example of the voltage switching circuit 12C.

This voltage switching circuit 12 C-3 constitutes a PLL circuit having a large time constant by negatively inputting the oscillation output of the voltage controlled oscillator (V C 0) 13 C.

That is, the voltage switching circuit 12 C-3 includes a register 126 C, a 0 converter 127 C, a voltage controlled oscillator (VC 0) 128 C, and a comparator 122 C. The clock frequency instruction data issued from the CPU 11C is stored in the register 1226C. 0 The converter 1 2 7 (converts the value of the instruction data stored in the register 1 2 6 from a digital value to an analog value.

This analog output is input to the voltage controlled oscillator (VCO) 12 SC as its control voltage. The oscillation output frequency of the voltage-controlled oscillator (VCO) 128 C decreases as the analog output voltage rises. The frequency of the oscillation output of the voltage controlled oscillator (VC0) 128C is compared with the frequency of the clock CLK fed back from the voltage controlled oscillator (VC0) 13C by the comparator 1229C. The comparator 1229 C is set so that the oscillation output of the voltage controlled oscillator (.VCO) 128 C and the phase of the clock CLK fed back from the voltage controlled oscillator (VC 0) 13 match. Voltage controlled oscillator (VC0) Changes the control voltage to 13C. By this phase locked loop (PLL) control, the clock CLK output from the voltage controlled oscillator (VCO) 13 C is changed from high-speed clock to low-speed clock with the frequency and phase being continuous. Changed to lock.

? The operation of shifting to the sleep mode and the operation of returning from the sleeve mode in the portable computer according to the fourth embodiment will be described with reference to the flowchart of FIG. 33.

If the CPU 11C enters the key input wait state while executing the application program, for example, the routine of the interrupt waiting function is usually called by the application program. You. This function waiting for an interrupt

Provided by the BIOS program.

In the interrupt waiting function routine, the CPU 11C first determines whether or not a key input interrupt has occurred (step S11-3). This determination process is executed by the CPU 11C examining the cause of the interrupt when the interrupt signal INT is supplied to CPU 1] C. Whether or not the interrupt is caused by the key input interrupt request IRQ1 is determined, for example, by reading the status register of the interrupt controller 17C. When a key input interrupt occurs, the CPU 11C reads the key code from the keyboard controller (KBC) 15C (step S12-3), and then executes the application program. People.

On the other hand, if no key input interrupt has occurred, the CPU 11C recognizes that the sleep mode setting conditions have been satisfied, and executes a subroutine for setting the sleep mode. Here, the CPU 11C outputs the clock CLK at high speed. In order to switch from the lock to the low-speed clock, data specifying the low-speed clock is transmitted to the voltage switching circuit 12C (step S13-3). As a result, the control voltage output from the voltage switching circuit 12C is gradually increased from the voltage V1 corresponding to the high-speed clock to the voltage V2 corresponding to the low-speed clock. VC 0) The frequency of the clock CLK output from 13 C is gradually reduced. As a result, the CPU 11C is set to the sleep mode operated by the low-speed clock CLK.

Thereafter, when the hardware interrupt signal INT from the interrupt controller 17C is input to the CPU 11C (step S14-3), the CPU 11C switches from the low-speed clock to the high-speed clock. In order to switch, data for designating a high-speed clock is transmitted to the voltage switching circuit 12C (step S15-3). As a result, the control voltage output from the voltage switching circuit 12C is gradually reduced from the voltage V2 corresponding to the low-speed clock to the voltage V1 corresponding to the high-speed clock. (VC 0) The frequency of the clock CLK output from the 13 C is gradually increased. As a result, the clock CLK becomes a high-speed clock, and the CPU 11C returns from the sleep mode to the normal mode. Then, the CPU 11C executes an interrupt process corresponding to the hardware interrupt signal IINT (step S16-3).

As described above, in the portable computer according to the fourth embodiment, the oscillation of the voltage-controlled oscillator (VC 0) 13 C The output is used as the clock CLK of the CPU 11C, and the clock CLK can be set to, for example, a high-speed clock by variably setting the oscillation frequency of the voltage-controlled oscillator (VCO) 13C. Switch from lock to low speed clock. In this case, the frequency of the oscillation output of the voltage controlled oscillator (VC 0) 13 C is gradually changed by the control of the voltage switching circuit 12 C. This eliminates problems such as phase discontinuity when the clock C'LK switches from a high-speed clock to a low-speed clock, and guarantees the operation of the CPU 11C. . Therefore, the clock of the CPU 11C can be switched in a state where the operation of the CPU 11C is guaranteed, so that the power consumption of the portable computer can be reduced and compatibility can be ensured.

Such a clock switching system is particularly suitable for realizing the sleep mode function of a CPU that has an internal oscillator including a PLL, but does not have an internal oscillator and is synchronized with an external clock. Of course, even when applied to a CPU that operates in such a manner, the power consumption can be reduced without causing a malfunction as well.

Also, here, switching between two clocks, a high-speed clock and a low-speed clock, has been described. However, if the range of variation of the oscillation frequency of the voltage-controlled oscillator used is within the range, Operation clocks can be switched between three or more clocks with different speeds. In this case, the power consumption can be reduced by lowering the clock frequency, and it is preferable to use the slowest clock in sleep mode.

In addition, to maintain the sleep mode for a longer period, The system timer interrupt request IRQ 0 during the wake mode is preferably masked by the interrupt controller 17C. In this way, the system timer interrupt request IRQ0 generated in units of 55 ms is prohibited. For this reason, the sleep mode period can be set to 55 ras or more, and the power consumption can be further reduced.

In this case, the operation of shifting the CPU 11C to the sleep mode and the operation of returning from the sleeve mode are performed as shown in FIG.

That is, in this case, before step S13-3 for transition to the sleep mode shown in FIG. 33, step S100-3 and step S101-3 are performed. Be executed. In step S100-3, the CPU 11C sets the timer interrupt cycle of the real-time clock (RTC) 14C to 500 ms. This is realized by writing data indicating 500 ms to a predetermined register in the real-time clock (RTC) 14C. In step S101-13, the CPU 11C disables the timer interrupt of the system timer 16C, and enables the timer interrupt of the real-time clock (RTC) 14C. This is realized by writing predetermined mask data into the interrupt mask register of the interrupt controller (PIC) 17C.

As a result, in sleep mode, the system timer interrupt request IRQ 0 generated in units of 55 ms is disabled, Real-time clock (RTC) generated in 500 ms units 14C timer interrupt request IRQ 8 is enabled. For this reason, the set period of the sleep mode can be set to 55 ms or more, and the power consumption can be further reduced.

The reason for setting the timer interrupt cycle of the real-time clock (RTC) 14C to 500 ms here is to support the clock function of the application program. That is, if you are running an abbreviated program that has the function of digitally displaying the time on the display screen, you can update the timer count at least within 1 s. Needed. For this reason, here, the maximum setting period of the sleep mode is limited to 500 ms by using a timer interrupt in units of 50 Oms.

When the mode is shifted from the normal mode to the sleep mode, steps S102-3 are executed between steps S15-3 and S16-3. In step S102-3, the CPU 11C enables the timer interrupt of the system timer 16C and disables the timer interrupt of the real-time clock (RTC) 14C. . This is realized by writing predetermined mask data to the interrupt mask register of the interrupt controller (PIC) 17C. Thus, in the normal mode, the timer interrupt in 55 ms units becomes effective.

Next, a fifth embodiment of the present invention will be described.

The CPU screen of the portable computer according to the fifth embodiment. In this mode, the clock CLK is not switched, and the CPU maintains the Ha1t state. In the Halt state, no bus access is performed by the CPU, so that power consumption can be reduced without lowering the clock CLK frequency.

FIG. 35 shows the configuration of a portable computer according to the fifth embodiment. This portable computer is a computer that is driven by an AC commercial power supply or a battery that is removably attached to the computer itself, and has a CPU 11D, BIOS-ROM 12D, system timer 13D, Real-time clock (RTC) 14 D, keyboard controller (KBC) 15 D, programmable interrupt controller (PIC) 16 D, dynamic RAM (DRAM) 17 D Have.

The CPU 11D is in charge of controlling the entire system, and each component, that is, the BIOS-ROM 12D, the system timer 13D, and the real-time microcomputer are connected via the system bus 10D. Lock [RTC] 14D, Keyboard Controller (KBC) 15D Connected to Programmable Interrupt Controller (PIC) 16D and Dynamic RAM (DRAM) 17D. The CPU 11D includes, for example, the above-described microprocessor 80486, and includes an internal oscillator 11D including a PLL circuit in order to internally generate a high-speed clock. In other words, this CPU 11 D uses a clock several times the clock CLK to generate the internal oscillator 11 D. 内部生成内部生成構成構成構成構成

The CPU 11D determines whether or not the sleep mode setting conditions are set by executing a BI0S (Basic Input Output System) program called by the application program being executed. When the condition is satisfied, the Ha1t instruction is executed to stop the operation. The sleep mode setting condition is satisfied, for example, when the operator has not performed a key input operation for a certain period or more.

The system timer 13D is a timer that periodically generates a timer interrupt request IRQ0 at a period of, for example, 55 ms. This timer interrupt request IRQ0 is supplied to the interrupt controller 16D. The real-time clock (RTC) 14D is a module that implements a clock function and a calendar function. Its internal memory does not lose its contents even when the power is turned off. The power supply for backup is always supplied. The real-time clock (RTC) 14D periodically generates a timer interrupt request IRQ 8 at a period of, for example, 500 ms. This timer interrupt request IRQ 8 is supplied to the interrupt controller 16D. The keyboard controller (KBC) 15D is used to control the keyboard built into this portable computer, and scans the keyboard's keyboard matrix and uses it as a press key. Generate the corresponding key data (scan code). At this time, the keyboard controller (KBC) 15 D Generates a key input interrupt request I RQ 1 to notify the CPU 11 D This key input interrupt request IRQ 1 is supplied to the interrupt controller 16D.

The interrupt controller 16D supplies the hardware interrupt signal INT to CPU11D. That is, when the interrupt controller 16D receives one of the timer interrupt request IRQ0, the key input harmful input request IRQ1, and the timer interrupt request IRQ8, the interrupt controller 16D outputs the hardware interrupt signal INT. appear. In this case, one of the timer interrupt request IRQ0 and the timer interrupt request IRQ8 can be selectively masked by the interrupt mask register 61D in the interrupt controller 16D. The dynamic RAM (DRAM) 17 D is for storing application programs executed by the CPU 1 ID.

Next, with reference to the flowchart of FIG. 36, a description will be given of a transition operation to the sleep mode and a return operation from the sleep mode in the portable computer.

If the CPU 11D is in a state of waiting for a key input, for example, during the execution of the application program, an interrupt-waiting function routine is called by the application program. This interrupt waiting function is provided by the BIOS program.

In the interrupt waiting function routine, first, the CPU 11D determines whether a key input interrupt has occurred (step S11-4). This judgment processing is interrupted by CPU11D. When the only signal INT is supplied, the CPU 11D executes by checking the cause of the interrupt. Whether or not the interrupt is caused by the key input interrupt request (IRQ) is determined by reading the status register of the interrupt controller 16D, for example. When a key input interrupt occurs, the CPU 11D reads the key code from the keyboard controller (KBC) 15D (step S12-4), and then executes the application program. ^ z *> o

-If no key input interrupt occurs,

The CPU 11 D recognizes that the sleep mode setting condition has been satisfied, and executes processing for setting the sleep mode. Here, the CPU 11D first sets the timer interrupt cycle of the real-time clock (RTC) 14D to 500 ms (step S13-4). This is achieved by writing data indicating 500 ms to the RTC register 41D in the real-time clock (RTC) 14D. Next, the CPU 11D disables the timer interrupt of the system timer 13D and enables the timer interrupt of the real-time clock (RTC) 14D (step S14-4). This is realized by writing predetermined mask data to the interrupt mask register 61D of the interrupt controller (PIC) 16D.

Thereafter, the CPU 11D executes the HaΓt instruction (HLT) for stopping the operation (step S15-4). this The Halt instruction prevents CPϋ11D from using system bus 10D. What? 171 1 0 113 1 state is from the interrupt controller 16 D from the hardware interrupt signal

Maintained until INT is manually entered.

While CPU11D is in the Ha1t state, the system timer interrupt request IRQ0 generated in units of 55 ms is prohibited, and the real-time clock generated in units of 500 ms.

(RTC) 16 D timer interrupt request IRQ8 is enabled. Because of this, 111 110 11 £ 11 1: State can be maintained for more than 55 ms.

The reason for setting the timer interrupt cycle of the real time clock (RTC) 14D to 500 ms is to support the clock function of the application program. In other words, if an abbreviated program that has the function of digitally displaying the time on the display screen is running, it is necessary to update the timer count at least within 1 s. You. For this reason, the maximum setting period of the sleep mode is limited to 500 ms by using a timer interrupt of 500 ms units.

Thereafter, when the hardware interrupt signal INT from the interrupt controller 16D is input to the CPU 11D (step S16-4), the CPU 11D sets the timer of the system timer 13D. Enable interrupts and disable real-time clock (RTC) 14D timer interrupts (step S17-4). And the CPU 11D A predetermined interrupt process corresponding to the only signal INT is executed (step S18-4).

Next, an example of the configuration of the RTC register 41D of the real-time clock (RTC) 14D will be described. The RTC register 41D is composed of two 8-bit registers 411 and 412 shown in FIGS. 37 and 38, respectively.

In the register 411, the data U IP of MSB indicates whether or not the timer has been updated.

"1" indicates that the timer has been updated or is about to start, and "0" indicates that the timer has not been updated. The data RS3 to RS0 from the third bit to the zeroth bit are setting information indicating the timer interrupt cycle of the real-time clock (RTC) 14D. , RS 0-When "1 1 1 1", the interrupt cycle is 500 ras.

In the register 4 12, the data S ET of bit 7 is bit information indicating whether or not this is an update cycle.

When "1", the update cycle is interrupted and data setting is enabled. The sixth bit of data, PIE, is bit information that enables / disables periodic timer interrupt requests. When "1", periodic interrupt requests are enabled, and when "0", periodic interrupt requests are enabled. Prohibit the request. The fifth data AIE is bit information for enabling / disabling the alarm interrupt request. The fourth data UIE is bit information for enabling / disabling the update interrupt request. Details of other bit information can be found here. Is omitted.

Next, an example of the configuration of the interrupt mask register 61D of the interrupt controller 16D will be described. The interrupt mask register 61D is composed of two 8-bit registers 611, 612 shown in FIGS. 39 and 40, respectively. The second data {} is bit information for enabling / disabling the interrupt request IRQ 1 from the keyboard controller 15 D. When data Κ Β = "1", interrupt request IRQ1 is enabled, and when data KB = "0", interrupt request IRQ1 is disabled. The data STMR of the 0th bit is bit information that enables the interrupt request IRQ 0 from the system timer 13D and disables Z. When the data STMR = "1", the interrupt request IRQ 0 Is enabled and interrupt request IRQ 0 is disabled when the status is STMR- "0". O

In the register 6 12, the 0th data RTC is bit information that enables the timer interrupt request IRQ 8 from the real-time clock (RTC) 14 D and disables Z. Data RTC = "1" When, the timer interrupt request IRQ 8 is enabled, and when the data RTC = "0", the timer interrupt request IRQ 8 is disabled.

FIG. 41 shows an example of the configuration of the interrupt controller: 16D. Here, only the configuration for masking one of the two timer interrupt requests IRQ 0 and IR 08 is shown. Have been.

The interrupt controller 16D is provided with AND gates G1, G2 and OR gate G3. A timer interrupt request IRQ0 from the system timer 13D is input to the first input of the AND gate G1. The second input of the AND gate G1 is connected to a predetermined bit of interrupt mask register 61D (bit 0 of register 6111 in FIG. 39). The output of the AND gate G1 is supplied to the first input of the OR gate G3. A N D gate G 2nd :! The input is a timer interrupt request IRQ8 from the real-time clock 14D. The second input of the AND gate G2 is connected to a predetermined bit of the interrupt mask register 61D (the 0th bit of the register 6112 in FIG. 40). The output of the AND gate G2 is supplied to the second input of the OR gate G3.

As described above, in the fifth embodiment, by extending the Ha1t state of the CPU 11D, the power consumption of the CPU 11D can be simplified without switching the clock. With a simple configuration, it can be effectively reduced.

The configuration of the RTC register in FIGS. 37 and 38, the interrupt mask register in FIGS. 39 and 40, and the configuration of the interrupt controller in FIG. The same applies to the system of the four embodiments.

Although the embodiments of the present invention have been described with reference to the drawings, the technical scope of the present invention is not limited to these embodiments, and it is a matter of course that various modifications can be made. Industrial applicability

As described above, according to the present invention, the power consumption of the CPU can be efficiently reduced without causing a malfunction of the CPU, so that the present invention is particularly suitable for a battery-operated portable computer.

Claims

The scope of the claims

1. A portable computer having a CPU, a clock generation circuit for supplying a clock to the CPU, and various peripheral circuits connected to the CPU via a system bus. Means for judging whether or not a predetermined mode setting condition for setting the sleep mode is satisfied, and saving data of the register of the CPU to a memory in response to the satisfaction of the condition;

In response to the evacuation of the data, the reset signal supplied to the CPU is set to an active state, thereby resetting the CPU and stopping the clock supply. Means for stopping the clock,

In response to an interrupt request from the peripheral circuit to the CPU, the supply of the clock is restarted, and the CPU is restarted by setting the reset signal to an inactive state. Means,

Means for restoring data from the memory to the CPU in response to the setting of the reactive state of the reset signal.

2. The portable computer according to claim 1, wherein the peripheral circuit includes a timer for periodically issuing an interrupt request to the CPU in a first cycle.

3. A means for changing a cycle of an interrupt request issued from the timer from the first cycle to a second cycle longer than the first cycle in response to the saving of the data. No. The portable computer according to item 2.

4. A portable computer having a CPU, a clock generation circuit for supplying a clock to the CPU, and various peripheral circuits connected to the CPU via a system bus, wherein the CPU is Means for determining whether a predetermined mode setting condition for setting the sleep mode is satisfied, and for saving the data of the register of the CPU to the memory in response to the satisfaction of the condition; and responding to the saving of the data. Power reset means for resetting the CPU by setting a reset signal supplied to the CPU to an active state, and for stopping power supply to the CPU;

The power supply to the CPU is resumed in response to an interrupt request from the peripheral circuit to the CPU, and the reset signal is set to an inactive state.

Means to restart CPU,

5. Means for electrically isolating the CPU from the system bus to cut off current flowing from the peripheral circuit to the CPU via the system bus in response to the stop of power supply to the CPU. The portable computer according to claim 4, further comprising:

6. The peripheral circuit according to claim 4, wherein the peripheral circuit includes a timer for periodically issuing an interrupt request to the CPU in a first cycle. Portable computer.

7. Means for changing the cycle of an interrupt request issued from the timer from the first cycle to a second cycle longer than the first cycle in response to satisfaction of the sleep mode condition. The portable computer according to claim 6, comprising:

8. A CPU, various peripheral circuits connected to the CPU via a system bus, and a clock generation circuit for generating a first clock and a second clock having a lower frequency than the first clock. A portable computer having

Means for judging whether a predetermined mode setting condition for setting the CPU in the sleep mode is satisfied, and saving the data of the register of the CPU to the memory in response to the satisfaction of the condition; The reset signal supplied to the CPU is set to be active in response to the timing signal of step (1).

Resetting means for resetting CPU;

First clock switching means for switching a clock supplied to the CPU from the first clock to the second clock in response to a second timing signal;

Generating a first timing signal in response to the saving of the data, and generating the second timing signal by delaying the first timing signal by a predetermined time; A delay circuit,

In response to a third timing signal, a second clock switch that switches the clock supplied to the CPU from the second clock to the first clock. Means, Reset canceling means for restarting the CPU by setting the reset signal to an inactive state in response to a fourth timing signal;

The third timing signal is generated in response to an interrupt request from the peripheral circuit to the CPU, and the fourth timing is generated by delaying the third timing signal by a predetermined time. A second delay circuit for generating a signal

9. The portable computer according to claim 8, wherein said peripheral circuit includes a timer for periodically issuing an interrupt request to said CPU in a first cycle.

10. A method according to claim 9, further comprising: means for changing a cycle of an interrupt request issued from the timer from the first cycle to a second cycle longer than the first cycle in response to the data saving. The portable computer described in the section.

1 1. A portable computer with a CPU that operates at a speed corresponding to the clock supplied from the outside,

A voltage-controlled oscillator whose oscillation frequency is variably set according to the control voltage;

Voltage control means for increasing or decreasing the value of the control voltage supplied to the voltage controlled oscillator in response to a clock switching request from the CPU.

The oscillation output of the voltage controlled oscillator is applied to the CP Portable computer supplied as a computer.

12. The oscillation output of the voltage controlled oscillator is fed back to the voltage control means so that a phase locked loop is formed by the voltage controlled oscillator and the voltage control means. The portable computer according to item 1.

1 3. A portable computer with a CPU that can switch between normal operation mode and low current consumption mode.

First timer means for periodically generating an interrupt request in a first cycle;

Second timer means for periodically generating an interrupt request in a second cycle longer than the first cycle,

Means for generating a timer interrupt signal for switching the CPU from the low current consumption mode to the normal mode in response to an interrupt request from the first or second timer means;

When the CPU is in the low current consumption mode, the CPU disables the low current consumption mode so that an interrupt request of the first timer means is prohibited and an interrupt request of the second timer means is permitted. And an interrupt mask means for selectively masking an interrupt request of the first timer means in accordance with the mode or the normal operation mode.