JP2003006179A - Semiconductor device and method for controlling operation mode of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make compatible power reduction and high performance of a microprocessor, by realizing a versatile frequency control system, without depending on an OS. SOLUTION: A means which starts operation in a low frequency, when a job is executed and automatically makes the frequency high perform the job, when the job is executed continuously, after a predetermined time passes is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor and its control method.

[0002]

2. Description of the Related Art In recent years, the speed of microprocessors has been remarkably increased, and the speed has been doubled in about one year. On the other hand, the problem of increased power consumption has become apparent as speed increases. Particularly when the microprocessor is used in a mobile device system, the increase in power consumption shortens the battery life. In order to give the battery life the highest priority in the portable device system, the power consumption is reduced by operating the processor at a frequency lower than the maximum frequency that can be executed by the processor. However, this method does not allow the processor to perform sophisticated information processing.

To cope with such a problem, when the load executed by the processor is small, the power supply voltage and frequency are lowered to reduce the power consumption, and when the load is large, the power supply voltage and frequency are raised to improve the performance. A scheme has already been proposed.

As a conventional example of such a system, 2000
IEE, International, Solid, State, Circuit, Conference, Digest,
Of, Technical, Papers (2000, IEEE Internatio
nal Solid-State Circuits, Digest of Technical Paper
s) pp. 292-293. In this conventional example, the frequency and the power supply voltage are controlled according to the deadline required by the application executed by the processor. The operating system (hereinafter O
S) is used, and a system including a circuit for generating a power supply voltage capable of executing the required frequency, a power supply, and the like is proposed.

[0005]

In the above conventional example, since the OS is used to determine the optimum frequency, the following problems occur. (1) The OS needs a calculation for determining an optimum frequency for performing this control. Since the OS itself is run by the microprocessor, the microprocessor has an overhead for control and its power consumption increases. (2) In this control method, since both the microprocessor and the OS need to cooperate with each other, they cannot operate unless they are compatible with the same power supply frequency control system. However, in reality, various OSs and various microprocessors already exist in the world, and they are actually used in various devices. Actually these OS
Widespread application of this control method to microprocessors would lead to problems such as standardization.

Therefore, the present invention realizes a frequency control system having high versatility without depending on the OS, and achieves both low power consumption and high performance of the microprocessor.

[0007]

For this reason, the present invention uses the following means.

A semiconductor device having a processor for executing a job in which a plurality of instructions are continuously executed and a control unit for controlling an operation mode of the processor, wherein the control unit is provided when the processor starts executing the job. Sets the operation mode of the processor to the first mode, and after a lapse of a predetermined time after the processor starts executing the job, the control unit sets the operation mode of the processor to the second mode. Here, in the second mode, the processor is allowed to operate at a higher speed than the operating speed possible in the first mode. Specifically, the operating frequency of the second mode is set higher than that of the first mode, the operating frequency of the second mode is set higher than that of the first mode, and the power supply voltage is set higher than that of the first mode. Increase the operating frequency and decrease the absolute value of the substrate bias.

Further, the control unit can detect the state of the processor from the address of the pointer of the processor and the state of the control signal output to the clock supply circuit, and control the operation mode regardless of the OS operating on the processor. To

Further, information about a predetermined time to be changed from the first mode to the second mode is stored in an external ROM or a built-in non-volatile memory, and transferred to a register of a control unit at power-on or system reset. Thus, the predetermined time can be set to a time suitable for the application to be processed by the processor.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on Examples.

FIG. 1 is a waveform diagram showing an example of controlling both the power supply voltage and the frequency according to the first embodiment of the present invention.
In this example, the processor executes job 1, job 3, job 3. Here, the job is a substantially continuous instruction sequence executed by the processor.

Job 1 is started to be executed at time t0.
At this time, the processor starts execution at a low operating frequency fL and a low power supply voltage VL. After that, at time t1 when a certain time ta has elapsed, the processor detects the elapse of time ta and changes the power supply voltage and the frequency. After time t1, the processor executes job 1 with a high operating frequency fH and a high power supply voltage VH. Finally, the execution of job 1 ends at time t2. Similarly, job 2 starts at frequency fL and power supply voltage VL at time t3, and at time t4 when time ta elapses.
Therefore, the processor executes job 2 at the frequency fH and the power supply voltage VH. Job 2 ends at time t5. Next, job 3 starts at time t6. Job 3 starts at frequency fL and power supply voltage VL, but is a relatively short job,
The process ends without the time ta. That is, job 3 ends at time t6 without performing control to change the frequency and power supply voltage to frequency fH and power supply voltage VH.

The power consumption in this example is shown in FIG. It is well known that when the power of a CMOS circuit is P, its value is proportional to the product of the square of the frequency and the voltage, that is, P∝f * V ² .

As an example, it is assumed that the relationship of VH = 2VL and fH = 2fL is established.

In this case, the power consumption P1 when operating at the operating frequency fL and the power supply voltage VL is P1∝fL * VL ² , and the power consumption P2 when operating at the operating frequency fH and the power supply voltage VH is
The ^{P2αfH * VH 2 = 2fL * (} 2VL) 2 = 8P1. Thus, P1 is 1/8 the power of P2. In the method of simply lowering the frequency without lowering the power supply voltage, the power is reduced only in proportion to the frequency (1/2 in this example).
A method of controlling the power supply and the frequency at the same time is effective. The control method of controlling the power supply voltage and the frequency can reduce the average power consumption as the power consumption P1 is longer. Here, the mode of power P1 is defined as a low power mode, and the mode of power P2 is defined as a high speed mode.

In this control method, a predetermined time ta is set to distinguish between low power operation and high speed operation. It is in low power mode when you start to run a job. Since a job with a relatively light load completes execution in a short time in the low power mode, the execution is completed with small power consumption. On the other hand, in the case of a heavy load job, the job does not end during the low power mode period (time ta). Here, when a certain time ta is reached, the mode automatically shifts to the high speed mode. As a result, when the load is heavy, it is possible to operate at a high frequency, so that the maximum performance of the processor can be utilized. In addition, there may be a case where the job is continuously executed without interruption. In such a case, however, it is a case where the processor capacity is to be maximized and the high speed mode may be maintained.

The information on the time ta may be stored in a register or the like in the semiconductor integrated circuit. The hardware in the integrated circuit can monitor the passage of time ta and automatically shift from the low power mode to the high speed mode. Therefore, it is possible to achieve both low power consumption and high performance of the microprocessor by a simple method. FIG. 2 shows a configuration example of the hardware according to FIG.

The semiconductor integrated circuit 20 includes a processor (CPU) 25 for executing software, a controller 26 for controlling the operation mode of the processor, and a clock supply circuit (the clock supply circuit is represented by a PLL. ,
23) and a power supply circuit 24.
Further, the control unit 26 has a ta register 21 that holds information on the time ta and a control circuit 22 that controls the PLL 23 and the power supply circuit 24. The control circuit 22 monitors the execution status of the job, and when the job is started, the PLL 2
3 and the power supply circuit 24 to control the operating frequency f of the processor.
To fL and the power supply voltage Vdd to VL. Furthermore, the control circuit 2
2 compares the time ta held in the ta register 21 with the job execution time, and when the job execution time reaches ta, P
The frequency and the power supply voltage are set to fH and VH by controlling the LL 23 and the power supply circuit 24, respectively. When the job is completed, the frequency and power supply voltage are returned to fL and VL.

The power supply circuit 24 does not necessarily have to be provided in the semiconductor integrated circuit, and a power supply element capable of controlling the output voltage may be used. FIG. 3 shows another hardware configuration example. In this example, the hardware configuration of the system is shown in more detail. Reference numeral 1 is a semiconductor integrated circuit device, 2 is a power supply circuit, and 3 is a boot ROM.

The control method of the system is the same as the example shown in FIG. This example is characterized in that the power supply circuit 2 exists in a circuit different from the semiconductor integrated circuit device 1. The control circuit 4 of the semiconductor integrated circuit device 1 sends a control signal to the power supply circuit 2 to control the power supply voltage Vdd generated by the power supply circuit 2. Further, in this example, the boot ROM 3 and the semiconductor integrated circuit device 1 are connected, and the boot ROM 3 provides information necessary when the system is started up to the semiconductor integrated circuit device 1.
It works to take in. Information about the time ta may be stored in the boot ROM 3 and input to the register 5 when the system is powered on or when the system is reset. In addition,
The information on the time ta may be time information or the number of clocks. In the former case, the timer 6 may be used for the measurement, and in the latter case, the counter (not shown) may be used for the measurement. With this configuration, even when the OS is subsequently installed in the memory or the like of the semiconductor integrated circuit device 1, the operation of the present invention can be executed without depending on the OS.

Here, the boot ROM is generally an EEPROM.
In many cases, non-volatile memory such as is used, but any non-volatile storage medium can be used, such as flash memory, battery backup RAM, floppy disk, hard disk, etc. so that the contents are automatically read at system startup. It should be. Although the boot ROM is outside the semiconductor integrated circuit device 1 in the example of FIG. 3, a nonvolatile memory such as a flash memory formed on the semiconductor integrated circuit device 1 or a battery-backed RAM has the same function. May be.

FIG. 4 is a diagram showing another operation waveform of the present invention.

In the present invention, the power supply and frequency are controlled on a job-by-job basis. Here, the microprocessor is the OS
In the case of also executing the above, the contents of the job include the task of executing the application and the execution of the OS executed before and after the task. That is, in Job 1 as shown in FIG.
Then, the task of the application is executed by the instruction of the OS. When the task of the application is completed, the control is returned to the OS, so that the OS is executed.
After that, if there is no job to be executed, the processor becomes idle by the action of the OS. The idle state is a state where the pointer of the processor continues to access a specific memory address. An interrupt is required to return from here.

FIG. 5 is a diagram showing a hardware configuration of a system for realizing the operation waveforms shown in FIG. 4 without the action of the OS.

In the hardware configuration of FIG. 5, in addition to the hardware configuration of FIG. 3, an idle register 9 and a comparator 10 are newly inserted in the semiconductor integrated circuit device.

The operation of this embodiment is as follows. When the system is started up, the idle address is read from the boot ROM 3 into the idle register 9 and the processor 8. Further, the value of the time ta is read into the ta register 5. The processor 8 first starts executing the job 1 at time t0. At this time, the processor 8 operates at a low operating frequency.
Execute job 1 with fL and low power supply voltage VL. Job 1 includes execution of OS, execution of task 1, and execution of OS. However, the hardware cannot distinguish them. After starting the job 1, the control circuit 4 starts measuring the elapsed time of the job by the timer 6. The control circuit 4 changes the power supply voltage Vdd and the clock frequency f at the time t1 when the fixed time ta has elapsed, and the processor 8 executes the job 1 at the high operating frequency fH and the high power supply voltage VH. Finally, when the execution of job 1 ends at time t2, the OS specifies the idle state and enters the idle state. At this time, O
S becomes an idle state by setting a pointer to an idle address previously input from the boot ROM 3. Therefore, the control circuit 4 recognizes that the idle state has been entered by determining that the address stored in the idle register matches the address designated by the pointer. Upon receiving the coincidence determination, the control circuit 4 sets the frequency f and the power supply voltage Vdd to the frequency fL and the power supply voltage.
The semiconductor integrated circuit device goes into the power reduction mode by dropping each to VL. When the next job (job 2) is started, the pointer points to an address different from the idle state, so this is detected by the comparison circuit 10, and the control circuit 4 starts measuring the job execution time. Job 2 finished, job 3
The start and end of can be determined in a similar manner.

With this configuration, it becomes possible to recognize the idle state and execute the low power operation of the present invention without depending on the OS.

FIG. 6 is a diagram showing still another operation waveform of the present invention. This example shows a case where the sleep state is entered after the job is completed. The sleep state is that the processor 8 stops the PLL and enters an interrupt waiting state. Since the clock is stopped in the sleep state, power is not consumed during that time, and as shown in the graph of power consumption in the figure, it is possible to reduce the overall power consumption as compared with the idle state.

FIG. 7 is a diagram showing a hardware configuration of a system for realizing the operation waveforms shown in FIG. 6 without the action of the OS.

The hardware configuration of FIG. 7 is almost the same as the hardware configuration of FIG. 5, but the on / off signal of the PLL 7 generated by the processor 8 is also input to the control circuit. With this signal, it is possible to recognize whether or not it is in the sleep state. Therefore, the control circuit 4 uses the PLL 7
It is possible to recognize that the job has started when is turned on, and to control the power supply circuit 2 and the PLL 7 so as to increase the power supply voltage and the frequency when a certain time ta has elapsed. It should be noted that in the sleep state, only the supply of the clock may be stopped during the standby state without stopping the PLL 7 so that the effect of lowering the power consumption is lessened but the return to the normal state can be made faster. A similar configuration can be made by using the control signal, and this is also the case in the examples shown below.

FIG. 8 is a diagram showing the waveform of the present invention in more detail in view of the nature of the operation of each circuit of the semiconductor integrated circuit device. As shown in FIG. 8, one job is PLL settling time, OS execution, task execution at low frequency fL, change of power supply voltage during task execution at low frequency fL,
It consists of task execution at high frequency fH and OS execution.

When the processor is in sleep mode, the power supply voltage is
VL and PLL is stopped. When attempting to get out of this state by an interrupt, first try to operate the PLL. In the hardware of FIG. 7, the control circuit receives the control signal of the PLL, so that the counter starts measuring the job execution time from the time when the interrupt occurs.
However, the PLL does not normally stabilize its operation suddenly, and usually requires a settling time of several tens of microseconds. The frequency is set to fL during the settling time. After the settling time has elapsed, first the OS is fL
Run on. After that, the task issued by the OS is executed. Initially the task is executed at frequency fL,
If the job continues even after the lapse of a fixed time ta, the power supply voltage is first shifted from VL to VH by a signal from the control circuit 4. When the power supply voltage shifts to VH and becomes stable, the operating frequency shifts from fL to fH. With this configuration, it is possible to prevent a malfunction caused by the processor being driven at the high frequency fH while being supplied with the low power supply voltage VL. When the task ends, O
The S operates at the frequency fH, and shifts to the sleep state according to the OS command.

By controlling the power supply voltage and the frequency in this way, the present invention can be executed without malfunction according to the characteristics of each circuit in the semiconductor integrated circuit device.

FIG. 9 is a diagram showing still another operation waveform of the present invention. FIG. 6 is a waveform diagram when there are three types of frequencies, fL, fM, and fH, and three types of power supply voltages, VL, VM, and VH, corresponding to the respective frequencies. As described above, the method of the present invention is not limited to two types of power sources and two types of frequencies. In this case, two types of time are set in advance: ta, which is a period of operation at the frequency fL and the power supply voltage VL, and tb, which is a period of operation at the frequencies fL and fM and the power supply voltages VL and VM. As shown in this waveform diagram, job 1 starts at time t0 with frequency fL and power supply voltage VL. After that, job 1 does not end even if the time ta elapses. Therefore, the operation is continued by changing the frequency fM and the power supply voltage VM, and the operation ends at the frequency and power supply voltage. The next job 2 is the same as job 1 at time t3.
Start with frequency fL and power supply voltage VL. After that, the job does not end even if the time ta elapses, so frequency fM and power supply voltage VM
Change to and continue operation. Predetermined time tb
Since it does not end even after the passage of, the job 2 is ended by continuing the execution at the frequency fH and the power supply voltage VH. In this way, it is possible to increase the types of power supply voltage and frequency and perform fine control. Further, it is not necessary that the power supply voltage and the frequency have a one-to-one correspondence such as two kinds of power supply voltage and three kinds of frequency. However, as described with reference to FIG. 8, the mode (combination of power supply voltage and frequency) is set so as not to supply a frequency higher than the operating speed possible with the supplied power supply voltage. There is a need.

FIG. 10 is a diagram showing operation waveforms when the present invention is used for executing a specific application, and is an embodiment for specifically explaining the effect of the present invention.

Recently, in portable devices such as mobile phones,
Video decoding and encoding has come to be performed. The characteristics of performing decoding and encoding of moving images with a microprocessor are that the job is performed periodically, and while most jobs are light jobs, there are jobs that sometimes require a very large amount of calculation. It is to be.

For example, in the case of decoding MPEG data of 30 frames / sec, the execution cycle of the job is 33
ms. In the MPEG data compression method, since the first frame is information in which the entire screen is compressed, a considerable amount of calculation is required to decode this. On the other hand, after the second frame, there is continuity between the frame images for a while, and only the difference from the previous frame needs to be calculated, so the calculation amount is relatively small. In this embodiment, this situation is illustrated.

Job 1 processes the first frame. At first, the processing is started at the frequency fL and the power supply voltage VL, but since the calculation amount of job 1 is large, the frequency is set when the time ta elapses.
fH and power supply voltage VH are changed to continue the processing, and the processing is ended. Here, the frequency fL is 1/2 of the frequency fH, and the time ta
Is 17.5 ms which is 1/2 of the cycle T (33 ms). The frequency up to time ta is fH / 2 and the frequency from time ta to time T is fH, so the average frequency in period T is 3fH /
It becomes 4. Therefore, according to the present scheme, assuming that the frequency fH is the maximum frequency that can be achieved by the microprocessor, it is the same as operating at a frequency of 75% of the average frequency.

On the other hand, assuming that the calculation of the second frame, the third frame, and the fourth frame is job 2, job 3, and job 4, respectively, the respective calculation amounts are small, so that the calculation can be completed within time ta. . Therefore,
The calculation after the second frame can maintain the frequency fL and the power supply voltage VL. The power during this period is 1/8 of the maximum power (12.5
%). As described above, according to the present invention, it is possible to achieve 75% of the maximum performance of the microprocessor while keeping the power consumption in the low power mode at 12.5% of the maximum.

FIG. 11 shows operation waveforms when a plurality of applications run on the CPU at the same time using the multitasking OS.

In the case of the multi-task OS, each application is divided into jobs and executed by the processor. The amount of calculation for each job depends largely on the nature of the application. For example, if the application is decoding compressed video and decoding compressed audio respectively, decoding the video requires a larger amount of calculation, and thus the length of the decomposed job increases. It is expected that. On the other hand, when decoding moving images, there is a wide range of variation between jobs. In such a case, if a setting time for changing the frequency and the power supply voltage is set to be relatively long for a moving image application, most jobs are completed before reaching the setting time, which can contribute to low power consumption.

In the example of FIG. 11, jobs 1 and 3 are jobs for application A, and jobs 2 and 4 are jobs for application B. At this time, the shorter set time tA is applied to the job 1 of the application A, and the longer set time tB is applied to the job of the application B. As described above, in the case of multitasking, the power consumption can be effectively reduced by setting the design time according to the property of the application. In this case, the ta register (FIG. 2, FIG. 3, FIG. 5, FIG. 7) requires the information of the set time tA and the information of the set time tB, respectively.

FIG. 12 is a waveform diagram in the case where the power source voltage is fixed and the substrate bias is controlled simultaneously with the frequency as the second embodiment of the present invention.

In the example shown in FIG. 12, at the start of a job, a low frequency fL and a deep substrate bias are supplied to the processor. Then, after the time ta has passed, the high frequency
Supply fH and shallow substrate bias. As a deep substrate bias, VbbNV is applied to the substrate or well of an NMOS transistor and VbbPV to the substrate or well of a PMOS transistor that form a processor. As the shallow substrate bias, the substrate potential having an absolute value smaller than the absolute value of the substrate potential applied as the deep substrate bias is applied. For example, 0 for the substrate or well of the NMOS transistor.
A power supply potential (Vdd) is applied to the substrate or well of the V and PMOS transistors.

When a deep substrate bias is applied, the threshold voltage rises and the operating frequency falls, but the leak current decreases, so the power is reduced. On the other hand, when a shallow substrate bias is applied, the threshold voltage decreases and the operating frequency increases, but the leak current increases and the power increases. The relationship between the operating speed and the power consumption is the same as when the frequency and the power supply voltage are controlled. Therefore, also by the control example of FIG. 12, it is possible to realize a frequency control method having high versatility without depending on the OS and to achieve both low power consumption and high performance of the microprocessor.

It should be noted that the second embodiment is also shown in FIG.
It can be realized by the hardware configuration as shown in FIGS. 3, 5, and 7. That is, a substrate bias generating circuit may be provided instead of the power supply circuit to generate a substrate bias as shown in FIG.

Further, although an example of controlling the power supply voltage and the frequency is shown as the first embodiment, it is possible to control only the frequency. Although the effect of low power consumption is smaller than that of the first embodiment, the structure can be simplified. In this case,
This can be realized by removing the control of the power supply circuit from the hardware configuration as shown in FIGS. 3, 5, and 7.

[0049]

According to the present invention, it is possible to realize a frequency control system having high versatility without depending on the OS and to achieve both low power consumption and high performance of the microprocessor.

[Brief description of drawings]

FIG. 1 is a waveform diagram showing an example of power supply-frequency control according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of hardware for implementing the present invention.

FIG. 3 is a diagram showing another configuration example of hardware for carrying out the present invention.

FIG. 4 is a waveform diagram showing another example of the power supply-frequency control according to the first embodiment of the present invention.

FIG. 5 is a diagram showing another configuration example of hardware for implementing the present invention.

FIG. 6 is a waveform diagram showing another example of the power supply-frequency control according to the first embodiment of the present invention.

FIG. 7 is a diagram showing another configuration example of hardware for carrying out the present invention.

FIG. 8 is a diagram showing in detail a waveform diagram of power supply-frequency control according to the first embodiment of the present invention.

FIG. 9 is a waveform diagram showing another example of the power supply-frequency control according to the first embodiment of the present invention.

FIG. 10 is a waveform diagram when the present invention is used to execute a specific application.

FIG. 11 is a waveform diagram when a plurality of applications simultaneously run on the CPU by the multitasking OS.

FIG. 12 is a substrate bias according to a second embodiment of the present invention.
It is a wave form diagram which shows the example of frequency control.

[Explanation of symbols]

1: semiconductor integrated circuit device, 2: power supply circuit, 3: boot R
OM, 4: control circuit, 5: register, 6: timer,
7: clock supply circuit, 8: processor, 9: idle register, 10: comparator, 11: controller.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B011 DC06 EA08 LL02 LL13                 5B062 AA03 AA05 GG01 HH02 HH06                 5B079 AA07 BA01 BB01 DD13

Claims (12)

[Claims] 1. A processor for executing a job in which a plurality of instructions are continuously executed, and a controller for controlling an operation mode of the processor, wherein the processor starts execution of the job. The control unit sets the operation mode of the processor to the first mode, and after a predetermined time elapses after the processor starts executing the job, the control unit sets the operation mode of the processor to the second mode. In the second mode, the processor is capable of operating at a higher speed than the operating speed possible in the first mode. 2. The processor according to claim 1, wherein in the first mode, the processor executes the job at a first operating frequency, and in the second mode, the processor has a higher operating frequency than the first operating frequency. A semiconductor device that executes the above job at an operating frequency of 2. 3. The processor according to claim 2, wherein in the first mode, the processor executes the job at a first power supply voltage, and in the second mode, the processor has a higher power supply voltage than the first power supply voltage. A semiconductor device that executes the above job with a power supply voltage of 2. 4. The method according to claim 2, wherein in the first mode, a first substrate potential is applied to a substrate or a well of a transistor forming the processor, and in the second mode, the substrate or a well of the transistor is applied to the substrate or well. A semiconductor device for applying a second substrate potential having an absolute value smaller than that of the first substrate potential. 5. The semiconductor device according to claim 1, wherein the control unit includes a control circuit that controls an operation mode of the processor, and a first register that stores information about the predetermined time. 6. The semiconductor device according to claim 5, wherein the information about the predetermined time is transferred from the external storage device to the first register when the power is turned on or the system is reset. 7. The processor according to claim 5, wherein the processor terminates the execution of the job when the pointer points to an idle address, and the control unit includes a second register for storing the idle address and the second register. The control circuit includes an idle address stored in a register and a comparator for comparing the pointer, the idle address is transferred from an external storage device to the second register when the power is turned on or the system is reset. Is a semiconductor device that receives the output indicating that the idle address stored in the second register and the pointer do not match, and determines that the processor has started executing the job. 8. The clock signal supply circuit for supplying a clock signal to the processor according to claim 5, wherein the processor outputs a control signal for controlling the supply of the clock signal to the processor, and the control circuit comprises: A semiconductor device that determines that the processor has started executing the job in response to the control signal that causes the processor to start supplying the clock signal to the processor. 9. The processor according to claim 1, wherein the processor executes a first job corresponding to processing of a first application and a second job corresponding to processing of a second application, and the processor When executing the first job, the control unit changes the operation mode of the processor from the first mode to the second mode after the first time has elapsed after the execution of the first job is started. When the processor executes the second job, the control unit causes the processor to operate after the second time different from the first time starts after the execution of the second job is started. A semiconductor device in which a mode is changed from the first mode to the second mode. 10. A method of controlling an operation mode of a semiconductor device including a processor for executing a job in which a plurality of instructions are continuously executed, wherein time information is stored in a register of the semiconductor device at power-on or system reset. A semiconductor device that starts execution of the job in a first operation mode, and changes from the first operation mode to the second mode after a lapse of a time indicated by the time information after starting the execution of the job Operating mode control method. 11. The operation mode control method for a semiconductor device according to claim 10, wherein the time information is transferred to the semiconductor device from an external nonvolatile memory or a nonvolatile memory built in the semiconductor device. 12. The processor according to claim 10, wherein the processor executes a first job corresponding to a process of a first application and a second job corresponding to a process of a second application, and the power is turned on or When the system is reset, the first job of the first job is registered in the register of the semiconductor device.
Of the first job for the second job is stored in the register of the semiconductor device when the power is turned on or the system is reset.
Of the first operation mode after the start of execution of the first job when the processor executes the first job. When changing to the second operation mode and the processor executes the second job, the first job is executed after the time indicated by the second time information has elapsed after the execution of the second job is started. A method for controlling an operation mode of a semiconductor device, wherein the operation mode is changed to the second operation mode.