JPS5954354A - Signal transmitting method - Google Patents

Signal transmitting method

Info

Publication number
JPS5954354A
JPS5954354A JP57163992A JP16399282A JPS5954354A JP S5954354 A JPS5954354 A JP S5954354A JP 57163992 A JP57163992 A JP 57163992A JP 16399282 A JP16399282 A JP 16399282A JP S5954354 A JPS5954354 A JP S5954354A
Authority
JP
Japan
Prior art keywords
signal
power supply
voltage level
supply voltage
display signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57163992A
Other languages
Japanese (ja)
Other versions
JPS645789B2 (en
Inventor
Hiroshi Hasegawa
浩 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57163992A priority Critical patent/JPS5954354A/en
Publication of JPS5954354A publication Critical patent/JPS5954354A/en
Publication of JPS645789B2 publication Critical patent/JPS645789B2/ja
Granted legal-status Critical Current

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  • Power Sources (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To prevent malfunction due to noise, by confirming that a power supply of an opposite device is at a normal voltage level, then receivig a signal from the opposite side. CONSTITUTION:The level of a power supply voltage of a power supply 15A is discriminated at a power supply voltage level discriminating circuit 16A, and attains to a digital power supply voltage level display signal SPA. The display signal SPA is transmitted to the opposite device 11B. The device 11B receives the display signal SPA at a discriminating circuit 17B and generates a gate signal SGB to switch a gate 18B. Further, a signal from the device 11A is received in response to the gate signal SGB.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は信号伝送方法、特に電源投入・切断時における
信号の伝送方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a signal transmission method, particularly to a signal transmission method during power-on/power-off.

(2)技術の背景 2つの装置(AおよびBとする)が伝送路を介して接続
されてなる信号伝送システムにおいて、装置Aおよび装
置Bがそれぞれ個別の電源によって駆動されることがあ
る。例えばこれら装置Aおよび装置Bが距離を隔てて置
かれる場合である。
(2) Background of the Technology In a signal transmission system in which two devices (referred to as A and B) are connected via a transmission path, device A and device B may be driven by separate power supplies. For example, if these devices A and B are placed apart from each other.

このような場合に、装置AおよびBが全く同じタイミン
グで電源投入・切断されることは殆どあり得ず、どちら
か一方が先に又は後に電源投入又は切断される。そうす
ると、一般に電源投入又は切断時には電源電圧にノイズ
が含まれることから、装置A又はBからのノイズが、既
に正常な動作状態にある、すなわち電源電圧が確定して
いる状態である相手方の装置(B又はA)に受信され、
誤動作を誘起することがある。
In such a case, it is almost impossible for devices A and B to be powered on or powered off at exactly the same timing, and one of them is powered on or powered off first or later. In this case, since noise is generally included in the power supply voltage when the power is turned on or turned off, noise from device A or B may be transmitted to the other device (which is already in a normal operating state, that is, whose power supply voltage has been determined). received by B or A),
It may cause malfunction.

従って、装置の電源投入・切断時には何らかのノイズ対
策が必要とされる。本発明は、このようなノイズ対策を
講じた信号伝送方法について言及するものである。
Therefore, some kind of noise countermeasure is required when powering on and off the device. The present invention refers to a signal transmission method that takes such noise countermeasures.

(3)従来技術と問題点 従来、装置Aおよび装置B間における上記ノイズ対策と
しては、これら装置間のプロトコルにおいて信号の組合
せに冗長性をもたせるという方法が採られていた。すな
わち、送信側より動作シーケンスの開始時において予め
定めた信号パターンを送信し、この信号パターンに合わ
ない信号を受信したときはこれをノイズであると判断し
、このような信号は受信側で受付けないようにするとい
うものである。然しながら、このようなノイズ対策には
2つの問題点がある。第1の問題点は、上記信号パター
ンを必ず動作シーケンスの開始時に発信するというのは
、該動作シーケンスに制約を課することになり、結局汎
用性を減じそして如何なる装置にも適用できるという自
由度を失うことになることである。第2の問題点は、装
置Aおよび装置Bが、中央処理装置(CPU)と入出力
装置(I/O)の間に布線された伝送路内に挿入される
ような場合、これら装置A又はBから発信された前記信
号パターンが、該CPUあるいはI/Oにおいて受信さ
れたときに、これらCPUあるいはI/Oに誤作動を生
じさせないような対策を予め講じておかなければならな
いことである。なお、上述のように伝送路内に装置Aお
よびB(あるいはこれ以上の数の装置でもよい)を挿入
するというケースは、CPUおよびI/O間の距離が遠
く隔たっているような場合にしばしば見られ、いわば信
号伝送における中継増幅ならびにインターフェースの役
割を果すべく挿入されることが多い。
(3) Prior Art and Problems Conventionally, as a countermeasure against the above-mentioned noise between device A and device B, a method has been adopted in which redundancy is provided in the combination of signals in the protocol between these devices. In other words, the transmitting side transmits a predetermined signal pattern at the start of an operation sequence, and when a signal that does not match this signal pattern is received, it is determined to be noise, and such a signal is not accepted by the receiving side. The idea is to make sure that there is no such thing. However, such noise countermeasures have two problems. The first problem is that if the above signal pattern is always transmitted at the beginning of an operation sequence, it imposes restrictions on the operation sequence, which ultimately reduces its versatility and reduces the degree of freedom that it can be applied to any device. This means that you will lose the The second problem is that when device A and device B are inserted into a transmission path wired between a central processing unit (CPU) and an input/output device (I/O), Or, measures must be taken in advance to prevent the CPU or I/O from malfunctioning when the signal pattern transmitted from B is received by the CPU or I/O. . Note that the case of inserting devices A and B (or more devices) into the transmission path as described above is often done when the distance between the CPU and I/O is large. It is often inserted to play the role of relay amplification and interface in signal transmission.

(4)発明の目的 本発明は上述第1および第2の問題点を同時に解決する
ことのできる信号伝送方法を提案することを目的とする
ものである。
(4) Purpose of the Invention The object of the present invention is to propose a signal transmission method that can simultaneously solve the first and second problems mentioned above.

(5)発明の構成 上記目的を達成するため本発明は、相互に信号の授受を
行う装置Aおよび装置Bにおける信号伝送方法において
、装置A(又はB)は、装置B(又はA)の電源が正規
の電圧レベルにあることを確認した上で装置B(又はA
)からの信号を受付けるようにしたことを特徴とするも
のである。
(5) Structure of the Invention In order to achieve the above object, the present invention provides a signal transmission method in a device A and a device B that mutually exchange signals, in which the device A (or B) is connected to the power source of the device B (or A). is at the correct voltage level, then connect device B (or A
) is characterized in that it accepts signals from.

(6)発明の実施例 第1図は本発明の方法を適用した1システム例を示すブ
ロック図である。本図のおいて、11Aおよび11Bは
相互に信号の授受を行う装置(A)および装置(B)で
あり、両者の間は伝送路12によって結ばれる。装置1
1Aおよび11Bは、例えば中央処理装置(CPU)1
3と入出力装置(I/O)14の間の伝送路内に挿入さ
れる。このようにするのは、既述のとおり、CPU13
とI/O14との間の伝送距離を伸ばすためである。た
だし、本発明の要旨は、装置11Aおよび装置11Bな
らびに伝送路12のみが存在する場合にも勿論適用でき
る。この場合は装置11AがCPU、装置11BがI/
Oとそれぞれみなせば良い。あるいは装置11A,11
Bが共にCPU又はI/Oであると考えても良い。
(6) Embodiment of the Invention FIG. 1 is a block diagram showing an example of a system to which the method of the invention is applied. In the figure, 11A and 11B are a device (A) and a device (B) that mutually exchange signals, and a transmission line 12 connects them. Device 1
1A and 11B are, for example, a central processing unit (CPU) 1
3 and an input/output device (I/O) 14. As mentioned above, this is done by the CPU 13.
This is to extend the transmission distance between the I/O 14 and the I/O 14. However, the gist of the present invention can of course be applied to the case where only the device 11A, the device 11B, and the transmission path 12 are present. In this case, device 11A is the CPU, device 11B is the I/
You can consider each as O. Or devices 11A, 11
Both B may be considered to be CPUs or I/Os.

ところで、装置11Aおよび11Bは、それぞれ個別の
電源(P)15Aおよび15Bで駆動されるものとする
と、その投入又は切断時におけるノイズにより既述の問
題点が生ずる。このノイズは第2図のa)に示される。
By the way, if the devices 11A and 11B are driven by separate power supplies (P) 15A and 15B, the above-mentioned problem occurs due to noise when the devices are turned on or turned off. This noise is shown in FIG. 2a).

第2図は本発明の方法を説明するために用いる波形図で
ある。第2図のa)は電源電圧の波形を例示したもので
あり、電源投入(Pon)の際と電源電圧(Poff)
の際には,殆どの場合ノイズNを伴う。ノイズNの発生
原因については種々考えられるが例えば、電源回路内の
各種スレッショルドを通じて規定の電源電圧まで立上が
ることによるものと考えられる。いずれにしても、この
ようなノイズNが相手方装置に伝われば誤作動を誘起す
ることは明らかである。
FIG. 2 is a waveform diagram used to explain the method of the present invention. Figure 2 a) shows an example of the waveform of the power supply voltage.
In most cases, noise N is accompanied. There are various possible causes of noise N, but for example, it is thought that it is caused by rising to a specified power supply voltage through various thresholds in the power supply circuit. In any case, it is clear that if such noise N is transmitted to the other party's device, it will induce malfunction.

そこで本発明は、相手方装置の電源状態を監視し、相手
方装置が正常な電源状態にないときはこの相手方装置か
らの信号を受付けないようにする。
Therefore, the present invention monitors the power state of the other party's device and does not accept signals from the other party's device when the other party's device is not in a normal power state.

すなわち、正常な電源状態にない装置11A(又は11
B)からの各種信号、例えばコマンドデータ、ステイタ
ス情報あるいはデータ等の信号は、I/O14(又はC
PU13)へは伝送されないことになり、誤作動は防止
される。実施例によれば、電源15A(15B)の電源
電圧は電源電圧レベル判別回路16A(16B)によっ
てレベル判定され、ディジタルの電源電圧レベル表示信
号SPA(SPB)となる。電源電圧レベルが正規の電
圧レベル(第2図a)のL)以上にあれば論理“1”、
それ以下であれば論理“0”であり、従って第2図b)
の如き表示信号SPA(SPB)が得られる。表示信号
SPA(SPB)は、相手方装置11B(11A)へ送
信される。
In other words, the device 11A (or 11
Various signals such as command data, status information, or data from I/O 14 (or C
The data will not be transmitted to the PU 13), and malfunctions will be prevented. According to the embodiment, the power supply voltage of the power supply 15A (15B) is level determined by the power supply voltage level determination circuit 16A (16B), and becomes a digital power supply voltage level display signal SPA (SPB). If the power supply voltage level is above the normal voltage level (L) in Figure 2 a), logic “1”;
If it is less than that, it is logic "0", therefore, Fig. 2b)
A display signal SPA (SPB) as shown below is obtained. The display signal SPA (SPB) is transmitted to the other party's device 11B (11A).

相手方装置11B(11A)では、表示信号SPA(S
PB)を判定回路17B(17A)において受信し、ゲ
ート18B(18A)を開閉するためのゲート信号SG
B(SGA)を発生する。第3図は第1図における判定
回路(17A,17B)の一例を示すブロック図である
。判定回路17Aおよび17Bは全く同一の構成である
から、判定回路17Bについて例示する。判定回路17
Bはカウンタ31およびROM(read only 
memory)32からなる。カウンタ31は論理“1
”の表示信号SPAを受信し続ける限り、その計数値を
カウントアップするが、1ビットでも論理“0”の表示
信号SPAを受信すれば、計数値を瞬時に零へクリアす
る。カウンタ31の計数値(出力)はROM32へ入力
され、ROM32は該計数値が予め定めた値Cより大に
なると論理“1”のゲート信号SGBを出力する。一方
、該計数値が零になると瞬時に論理“0”のゲート信号
SGBを出力する。
In the other party device 11B (11A), the display signal SPA (S
PB) is received in the determination circuit 17B (17A), and a gate signal SG for opening/closing the gate 18B (18A)
Generate B(SGA). FIG. 3 is a block diagram showing an example of the determination circuit (17A, 17B) in FIG. 1. Since the determination circuits 17A and 17B have exactly the same configuration, the determination circuit 17B will be exemplified. Judgment circuit 17
B is a counter 31 and a ROM (read only).
memory) consists of 32. Counter 31 is logic “1”
As long as the display signal SPA of "" continues to be received, the count value is counted up, but if even one bit of the display signal SPA of logic "0" is received, the count value is instantly cleared to zero. The numerical value (output) is input to the ROM 32, and the ROM 32 outputs a logic "1" gate signal SGB when the counted value becomes larger than a predetermined value C. On the other hand, when the counted value becomes zero, the logic "0'' gate signal SGB is output.

このような判定回路17B(17A)の採用により、第
2図c)に示すようなゲート信号SGB(SGA)が得
られる。同図c)において、TCは、前述の予め定めた
値Cに至るまでの期間を示す。
By employing such a determination circuit 17B (17A), a gate signal SGB (SGA) as shown in FIG. 2c) can be obtained. In c) of the same figure, TC indicates the period until the aforementioned predetermined value C is reached.

期間TCを経れば、電源電圧は十分に立上がり、装置の
正常な動作状態を確保できる。
After the period TC, the power supply voltage rises sufficiently and the normal operating state of the device can be ensured.

一方、電源切断(Poff)の際にはゲート信号SGB
(SGA)は、信号SPAの一回目の論理“0”で即座
に論理“0”となる。このようなゲート信号SGB(S
GA)をゲート18B(18A)に用いることにより、
例えば、電源電圧が十分に立上っていない装置11Bか
らの信号は、装置11Aのゲート18Aによって受付け
られず、電源投入時のノイズNを含む装置11Bからの
信号は装置11A内は勿論、CPU13へも伝わらない
。このことは、装置11Aの電源電圧が十分に立上って
いないときも同じであり、ノイズを含む装置11Aから
の信号は装置11B内は勿論、I/O14へも伝わらな
い。
On the other hand, when the power is turned off (Poff), the gate signal SGB
(SGA) immediately becomes logic "0" when the signal SPA becomes logic "0" for the first time. Such a gate signal SGB(S
By using GA) for the gate 18B (18A),
For example, a signal from the device 11B whose power supply voltage has not risen sufficiently will not be accepted by the gate 18A of the device 11A, and a signal from the device 11B that includes the noise N when the power is turned on will not only be transmitted to the CPU 13 within the device 11A. I can't even get it across. This is the same when the power supply voltage of the device 11A is not sufficiently raised, and the signal from the device 11A containing noise is not transmitted to the I/O 14 as well as inside the device 11B.

一方、例えば装置11Bの電源切断(Poff)の際に
は、装置11A内のゲート18Aは即座に閉となり、電
源切断時に発生するノイズNを含む装置11Bからの信
号は装置11A内は勿論、CPU13へも伝わらない。
On the other hand, for example, when the power of the device 11B is turned off (Poff), the gate 18A in the device 11A is immediately closed, and the signal from the device 11B containing the noise N generated when the power is turned off is transmitted not only to the inside of the device 11A but also to the CPU 13. I can't even get it across.

このことは装置11Aの電源切断の場合についても同じ
であり、ノイズを含む装置11Aからの信号装置11B
内は勿論、I/O14へも伝わらない。なお、19A,
19Bは伝送すべき信号のドライバ回路である。
This also applies to the case where the device 11A is powered off, and the signal from the device 11A containing noise is transmitted to the device 11B.
Of course, it is not transmitted to the I/O14 either. In addition, 19A,
19B is a driver circuit for a signal to be transmitted.

第1図では、伝送路12が多芯ケーブルで構成される例
を示したが、他の例も可能であり、伝送路の形態に左右
されない。
Although FIG. 1 shows an example in which the transmission line 12 is formed of a multi-core cable, other examples are also possible and are not affected by the form of the transmission line.

第4図は第1図の伝送路を簡潔化した1システム例を示
すブロック図である。この簡潔化は、いわゆる時分割多
重伝送方式に基づき実現され、そのために、パラレル/
シリアル変換回路(P/S)41A,41Bとシリアル
/パラレル変換回路(S/P)42A,42Bが導入さ
れる。然し、本発明の方法は、そのまま適用できる。
FIG. 4 is a block diagram showing an example of a system in which the transmission path of FIG. 1 is simplified. This simplification is achieved based on the so-called time division multiplexing method, which allows parallel/
Serial conversion circuits (P/S) 41A, 41B and serial/parallel conversion circuits (S/P) 42A, 42B are introduced. However, the method of the present invention can be applied as is.

(7)発明の効果 以上説明したように本発明によれば、既述の第1および
第2の問題点を解決することのできる信号伝送方法が実
現される。
(7) Effects of the Invention As described above, according to the present invention, a signal transmission method capable of solving the first and second problems described above is realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の方法を適用した1システム例を示すブ
ロック図、第2図は本発明の方法を説明するために用い
る波形図、第3図は第1図における判定回路(17A,
17B)の一例を示すブロック図、第4図は第1図の伝
送路を簡潔化した1システム例を示すブロック図である
。 11A,11B…装置、12…伝送路、15A,15B
…電源、16A,16B…電源電圧レベル判別回路、1
7A,17B…判定回路、18A,18B…ゲート、S
PA,SPB…電源電圧レベル表示信号、SGA,SG
B…ゲート信号■
FIG. 1 is a block diagram showing an example of a system to which the method of the present invention is applied, FIG. 2 is a waveform diagram used to explain the method of the present invention, and FIG. 3 is a determination circuit (17A,
FIG. 4 is a block diagram showing an example of a system in which the transmission path of FIG. 1 is simplified. 11A, 11B...device, 12...transmission line, 15A, 15B
...Power supply, 16A, 16B...Power supply voltage level discrimination circuit, 1
7A, 17B...judgment circuit, 18A, 18B...gate, S
PA, SPB...power supply voltage level display signal, SGA, SG
B...Gate signal■

Claims (1)

【特許請求の範囲】[Claims] 1.相互に信号の授受を行い且つそれぞれ個別の電源で
駆動される装置Aおよび装置Bでの信号伝送方法におい
て、該装置Aおよび装置Bはそれぞれ、前記電源が正規
の電圧レベル以上であることを示す論理“1”又はその
正規の電圧レベル以下であることを示す論理“0”から
なる電源電圧レベル表示信号を発生し且つ互いに相手方
の該装置A又は装置Bからの該電源電圧レベル表示信号
を受信して監視するようにし、前記装置Aおよび装置B
の一方の装置は、他方の装置からの前記電源電圧レベル
表示信号が論理“1”を所定期間継続して発生している
ことを確認してから当該他方の装置からの信号を受付け
るようにし、該電源電圧レベル表示信号が論理“0”を
発生したときは当該他方の装置からの信号の受付けを即
座に停止するようにしたことを特徴とする信号伝送方法
1. In a signal transmission method in a device A and a device B that mutually exchange signals and are each driven by separate power supplies, each of the devices A and B indicates that the power source is at a normal voltage level or higher. Generates a power supply voltage level display signal consisting of a logic "1" or a logic "0" indicating that the voltage is below the normal voltage level, and receives the power supply voltage level display signal from the device A or device B of the other party. and monitor the device A and device B.
one device accepts the signal from the other device after confirming that the power supply voltage level display signal from the other device continues to generate logic “1” for a predetermined period; A signal transmission method characterized in that when the power supply voltage level display signal generates logic "0", reception of a signal from the other device is immediately stopped.
JP57163992A 1982-09-22 1982-09-22 Signal transmitting method Granted JPS5954354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57163992A JPS5954354A (en) 1982-09-22 1982-09-22 Signal transmitting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57163992A JPS5954354A (en) 1982-09-22 1982-09-22 Signal transmitting method

Publications (2)

Publication Number Publication Date
JPS5954354A true JPS5954354A (en) 1984-03-29
JPS645789B2 JPS645789B2 (en) 1989-01-31

Family

ID=15784698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57163992A Granted JPS5954354A (en) 1982-09-22 1982-09-22 Signal transmitting method

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01218293A (en) * 1988-02-26 1989-08-31 Nec Corp Serial alarm system
JPH02173832A (en) * 1988-12-27 1990-07-05 Oki Electric Ind Co Ltd Duplex controller
JP2015002488A (en) * 2013-06-17 2015-01-05 富士ゼロックス株式会社 Communication device and communication control program

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5616223A (en) * 1979-07-20 1981-02-17 Fujitsu Ltd Interface circuit
JPS57120136A (en) * 1981-01-16 1982-07-27 Toshiba Corp Inhibiting system of input and output bus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5616223A (en) * 1979-07-20 1981-02-17 Fujitsu Ltd Interface circuit
JPS57120136A (en) * 1981-01-16 1982-07-27 Toshiba Corp Inhibiting system of input and output bus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01218293A (en) * 1988-02-26 1989-08-31 Nec Corp Serial alarm system
JPH02173832A (en) * 1988-12-27 1990-07-05 Oki Electric Ind Co Ltd Duplex controller
JP2015002488A (en) * 2013-06-17 2015-01-05 富士ゼロックス株式会社 Communication device and communication control program

Also Published As

Publication number Publication date
JPS645789B2 (en) 1989-01-31

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