JP2000172517A - Fail safe transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive, small-sized and light-weight circuit capable of stopping transmission by an electronic means not using a relay when the error is detected by inserting a buffer circuit between a processing circuit and a drive circuit and turning the output of an amplifier to the power source of the buffer circuit. SOLUTION: A master controller 1 provided on the cab of a railroad vehicle turns off a contact point in the inside by the operation of a handle and adds plural signals corresponding to it to input circuits 21 and 31. Also, the output of a transmission circuit 33 is added to a reception circuit 24 and the output of the transmission circuit 23 is added to the reception circuit 34 and the buffer circuit 9. Also, the output of the buffer circuit 9 is connected through the drive circuit 4 to a transmission line 8. To the transmission line 8, an inverter and a brake are connected. Further, the alternating output signals of timers 25 and 35 are added through a fail safe AND circuit 6 to an AC/DC conversion amplifier 7 and the output voltage is turned to the power source of the buffer circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fail-safe transmission circuit, and more particularly to a fail-safe transmission circuit used for transmitting control commands for railway vehicles.
It relates to an inexpensive, small and light circuit.

[0002]

2. Description of the Related Art A fail-safe transmission circuit described herein is a transmission circuit of a transmission system which does not transmit erroneous data in the event of any circuit failure. It is used when transmitting to the brakes.

[0003] For a fail-safe transmission circuit of a control command in a railway vehicle, see the 25th Railway Cybernetics Transactions, pp. 393 to 397, "Vehicle Information System (TIS) with Integrated Monitoring, Control Command Transmission and Vehicle Inspection Functions".
It is described in "November 1988" and the like, and includes a failure detection unit and a transmission stop unit when a failure is detected.

FIG. 2 is a diagram showing a configuration of a generally known fail-safe transmission circuit. That is, for detecting a failure, the dual processing circuits 2 and 3 are provided, and the outputs of the transmission circuits 23 and 33 of the respective systems are exchanged with each other to receive the reception circuits 24 and 34.
, And the respective processors 22 and 32 compare the transmission data with the reception data. If they are different, it is determined that a failure has occurred, and the alternating output signals of the timers 25 and 35 are stopped.

[0005] The transmission stop means at the time of failure detection in the processing circuit must be able to reliably stop the transmission when the alternating output signal stops, even if the failure itself occurs. For this reason, in the prior art, it is composed of a fail-safe AND circuit 6, an AC-DC conversion amplifier 7 having its output as an input, and a relay 5 driven by the amplifier output.
That is, as described above, when a failure is detected, the processing circuits 2 and 3
, The output of the AC-DC conversion amplifier 7 via the fail-safe AND circuit 6 is also stopped. Since the contact of the relay 5 is inserted between the drive circuit 4 and the transmission line 8, the transmission line is cut off and the transmission is stopped when a failure is detected.

[0006]

The relay inserted in the transmission line in the above-mentioned prior art is not only expensive but also large-sized.
This is an obstacle to reducing the size and weight of the circuit.

An object of the present invention is to provide an inexpensive, small and lightweight fail-safe transmission circuit which can stop transmission by electronic means without using a relay when an error is detected.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to insert a buffer circuit composed of a semiconductor element into a signal line between a processing circuit and a drive circuit for transmission, and to drive a power supply of the buffer circuit to drive a conventional relay. This is achieved by supplying from an AC-DC conversion amplifier.

Generally, in a semiconductor device such as a TTL, an output pin is in a high impedance state when power is cut off. Therefore, when the AC-DC conversion amplifier is stopped, the output terminal of the buffer circuit is in a high impedance state, and the output signal of the processing circuit is not transmitted to the modulation circuit, and the transmission is cut off.

[0010]

FIG. 1 is a diagram showing an embodiment of the present invention in a case where a control command from a driver's cab is transmitted to an inverter and a brake in a railway vehicle, in particular, and FIG. Components that are the same as the technology are denoted by the same symbols.

Note that the fail-safe transmission circuit described here is a transmission transmission circuit that never transmits erroneous data in the event of any failure. It is assumed that no failure will occur. That is, the processing circuits 2 and 3
The input circuits 21 and 31, the processors 22 and 32, the transmission circuits 23 and 33, and the reception circuits 24 and 3 have exactly the same configuration.
4. It consists of timers 25 and 35.

On the other hand, a master controller 1 provided in a driver's cab of a railway vehicle turns on and off internal contacts by operating a handle (not shown), and applies a plurality of signals to the input circuits 21 and 31 accordingly. The output of the transmission circuit 33 is applied to the reception circuit 24, and the output of the transmission circuit 23 is applied to the reception circuit 34 and the buffer circuit 9. The output of the buffer circuit 9 is connected to the transmission line 8 via a drive circuit. An inverter and a brake (not shown) are connected to the transmission path.

Further, the alternating output signals of the timers 25 and 35 are applied to an AC / DC conversion amplifier 7 via a fail-safe AND circuit 6, and the output DC voltage is used as a power supply for the buffer circuit 9.

In such a configuration, the processor 22
And 32 take in signals from the master controller 1 via input circuits 21 and 31, respectively, create transmission data based on the signals, and transmit the data via transmission circuits 23 and 33.
Further, the processors 22 and 32 exchange transmission signals and take in the signals via the reception circuits 24 and 34, respectively, and compare the transmission data with the reception data. Here, the processor 22
And 32 use the signal of the master controller 1 as a common input signal, and therefore are usually equal to the transmission data created by processing this signal.

However, if any failure occurs in the processing circuit 2 or 3 and the output data of the transmission circuit 23 or 33 contains an error, the failure can be detected because the comparison results do not match. Processors 22 and 32
Generates an alternating output signal via the timers 25 and 35 during normal times when no failure is detected, but stops it when a failure is detected. The reason why the alternate output signal is used instead of the normal high or low binary output signal is to prevent the failure state of the timer 25 or 35 itself from being erroneously output as normal. It is.

On the other hand, the fail-safe AND circuit 6
It is formed of a known fail-safe logic circuit, and generates an alternating signal only when both of the timers 25 and 35 generate an alternating output. The AC-DC conversion amplifier 7 is configured using a known fail-safe technique, and outputs a DC voltage only when an alternating signal is input,
The power supply for the buffer circuit 9 is used.

Therefore, in the normal state where neither of the processors 22 and 32 detects a failure, the transmission circuit 2
The output transmission signal of No. 3 is applied to the drive circuit 4 via the buffer circuit 9 and transmitted to the transmission line 8.

On the other hand, when the processor 22 or 32 detects a failure and stops the alternation signal of the timer 25 or 35, the output of the AC-DC conversion amplifier 7 also disappears, and the power supply of the buffer circuit 9 is lost. As a result, the transmission signal output from the transmission circuit 23 is not transmitted to the drive circuit 4, and the transmission stops.

In the above embodiment, the case where the buffer circuit 9 is inserted into the data line of the transmission signal has been described. A similar effect can be obtained even if the signal is inserted into a non-existing signal line.

In the embodiment, a buffer is inserted between the processing circuit and the drive circuit. However, the same effect can be obtained by supplying power to the drive circuit from an AC-DC conversion amplifier instead.

[0021]

According to the present invention, a fail-safe transmission circuit can be constituted by using a semiconductor element instead of a relay.
There is an effect that an inexpensive, small and lightweight circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a fail-sale transmission circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional fail-sale transmission circuit of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Master controller, 2, 3 ... Processing circuit, 4 ... Drive circuit, 6 ... Fail-safe and circuit, 7 ... AC-DC conversion amplifier, 8 ... Transmission line, 9 ... Buffer circuit.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Kazuhiro Yamada 1070 Ma, Hitachinaka City, Ibaraki Prefecture Inside the Mito Plant of Hitachi, Ltd. Mito factory F-term (reference) 5B034 AA02 CC01

Claims (2)

[Claims] 1. A dual processing circuit having a transmitting / receiving function and a comparing function of transmitted / received data, means for exchanging and receiving each other's transmission output signals, and one of the processing circuits A transmission drive circuit having an output signal as an input, in a transmission circuit including an amplifier controlled by a comparison result of transmission / reception data in the processing circuit, a buffer circuit is inserted between the processing circuit and the drive circuit; A fail-safe transmission circuit, wherein an output of the amplifier is used as a power supply of the buffer circuit. 2. A dual processing circuit having a transmission / reception function and a transmission / reception data comparison function, means for exchanging transmission output signals of the dual processing circuit with each other and receiving the signal, and one of the processing circuits In a transmission drive circuit having an output signal as an input, and a transmission circuit including an amplifier controlled by a comparison result of transmission / reception data in the processing circuit, an output of the amplifier is used as a power supply of the drive circuit. Fail-safe transmission circuit.